CS4382A-EQZ CIRRUS [Cirrus Logic], CS4382A-EQZ Datasheet - Page 29

• Manufacturer Part Number: CS4382A-EQZ
• Description: 114 dB, 192 kHz 8-channel D/A Converter
• Manufacturer: CIRRUS [Cirrus Logic]

DS618PP1
3.14.2.2 I
To read from the device, follow the procedure below while adhering to the control port Switching Spec-
ifications.
1. Initiate a START condition to the I
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the MAP,
or the default address (see section 3.14.1) if an I
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers.
Continue providing a clock and issue an ACK after each byte until all the desired registers are read, then
initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I
initiate a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I
Write instructions followed by step 1 of the I
desired, initiate a STOP condition to the bus.
S D A
S C L
N ote: If operation is a w rite, th is byte contain s the M em o ry A ddress P ointer, M A P.
Start
2
C Read
001100
Figure 17. Control Port Timing, I
ADDR
AD 0
R/W
2
C bus followed by the address byte. The upper 6 bits must be
2
ACK
2
C reads from other registers are desired, it is necessary to
C Read section. If no further reads from other registers are
2
C read is the first operation performed on the device.
DATA
1-8
N ote 1
2
C Mode
ACK
DATA
1-8
ACK
Stop
CS4382A
2
29
C