SN74LS256D MOTOROLA [Motorola, Inc], SN74LS256D Datasheet

SN74LS256D

Manufacturer Part Number

SN74LS256D

Description

DUAL 4-BIT ADDRESSABLE LATCH

Manufacturer

MOTOROLA [Motorola, Inc]

Datasheet

1.SN74LS256D.pdf (6 pages)

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DUAL 4-BIT

ADDRESSABLE LATCH

inputs; these include two Address inputs (A 0 , A 1 ), an active LOW Enable input

(E) and an active LOW Clear input (CL). Each latch has a Data input (D) and

four outputs (Q 0 – Q 3 ).

(Q 0 – Q 3 ) are LOW. Dual 4-channel demultiplexing occurs when the (CL) and

E are both LOW. When CL is HIGH and E is LOW, the selected output

(Q 0 – Q 3 ), determined by the Address inputs, follows D. When the E goes

HIGH, the contents of the latch are stored. When operating in the addressable

latch mode (E = LOW, CL = HIGH), changing more than one bit of the Address

(A 0 , A 1 ) could impose a transient wrong address. Therefore, this should be

done only while in the memory mode (E= CL = HIGH).

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial

PIN NAMES

A 0 , A 1

D a , D b

Q 0a – Q 3a ,

Q 0b – Q 3b

(74) Temperature Ranges.

The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control

When the Enable (E) is HIGH and the Clear input (CL) is LOW, all outputs

Serial-to-Parallel Capability

Output From Each Storage Bit Available

Random (Addressable) Data Entry

Easily Expandable

Active Low Common Clear

Input Clamp Diodes Limit High Speed Termination Effects

V CC

A 0

A 1

CONNECTION DIAGRAM DIP (TOP VIEW)

Address Inputs

Data Inputs

Enable Input (Active LOW)

Clear Input (Active LOW)

Parallel Latch Outputs (Note b)

D a

D b

Q 0a

Q 3b

Q 1a

Q 2b

Q 2a

Q 1b

Q 3a

Q 0b

GND

FAST AND LS TTL DATA

NOTE:

The Flatpak version

has the same pinouts

(Connection Diagram) as

the Dual In-Line Package.

HIGH

0.5 U.L.

1.0 U.L.

0.5 U.L.

10 U.L.

LOADING (Note a)

5-421

5 (2.5) U.L.

LOW

0.25 U.L.

0.5 U.L.

Q 0a Q 1a Q 2a Q 3a

D a

SN54/74LS256

ORDERING INFORMATION

ADDRESSABLE LATCH

LOW POWER SCHOTTKY

SN54LSXXXJ

SN74LSXXXN

SN74LSXXXD

LOGIC SYMBOL

A 0

A 1

DUAL 4-BIT

V CC = PIN 16

GND = PIN 8

2 1 15

Ceramic

Plastic

SOIC

CASE 751B-03

CASE 620-09

CASE 648-08

A 0

A 1

Q 0b Q 1b Q 2b Q 3b

CERAMIC

N SUFFIX

D SUFFIX

J SUFFIX

PLASTIC

SOIC

14 13

D b

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SN74LS256D Summary of contents

Page 1

DUAL 4-BIT ADDRESSABLE LATCH The SN54/74LS256 is a Dual 4-Bit Addressable Latch with common control inputs; these include two Address inputs ( active LOW Enable input (E) and an active LOW Clear input (CL). ...

Page 2

LOGIC DIAGRAM PIN 16 GND = PIN 8 = PIN NUMBERS ...

Page 3

GUARANTEED OPERATING RANGES Symbol Parameter V CC Supply Voltage T A Operating Ambient Temperature Range I OH Output Current — High I OL Output Current — Low DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE Symbol Symbol Parameter Parameter V IH Input ...

Page 4

AC SET-UP REQUIREMENTS ( Symbol Symbol Parameter Parameter t s Data Setup Time t s Address Setup Time t h Data Hold Time t h Address Hold Time t W Enable Pulse Width ...

Page 5

G - 0.25 (0.010 - SEATING -T- PLANE 0.25 (0.010) ...

Page 6

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of ...

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