CP80C88-2 INTERSIL [Intersil Corporation], CP80C88-2 Datasheet
CP80C88-2
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CP80C88-2 Summary of contents
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... Pb-Free Available (RoHS Compliant) TEMPERATURE PART NUMBER PART (8MHz) MARKING CP80C88-2 IP80C88-2 -40 to +85 -55 to +125 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners ...
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Pinouts 2 80C88 80C88 (40 LD PDIP CERIDP) TOP VIEW MIN MODE GND A14 2 39 A15 A13 3 38 A16/S3 A12 4 37 A17/S4 A11 5 36 A18/S5 A10 6 35 A19/S6 A9 ...
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Functional Diagram EXECUTION UNIT REGISTER FILE DATA POINTER AND INDEX REGS (8 WORDS) 16-BIT ALU FLAGS TEST INTR NMI RQ/GT0 HOLD HLDA BUS INTERFACE UNIT EXECUTION UNIT 3 80C88 BUS INTERFACE UNIT RELOCATION REGISTER FILE SEGMENT REGISTERS AND ...
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Pin Description The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers). PIN ...
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Pin Description The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/ are unique to the minimum mode are described; all other pin functions are as described above. PIN SYMBOL NUMBER TYPE MINIMUM MODE ...
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Pin Description (Continued) The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. ...
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Pin Description (Continued) The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above. ...
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OFFSET SEGMENT REGISTER FILE LSB CS WORD BYTE SS MSB DS ES FIGURE 1. MEMORY ORGANIZATION All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen ...
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AVAILABLE INTERRUPT POINTERS (224) RESERVED INTERRUPT POINTERS (27) DEDICATED INTERRUPT POINTERS (5) Bus Operation The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address ...
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V CC MN/MX 82C84A/85 CLK IO/M READY RD RES WR RESET RDY CLOCK GENERATOR INTA GND 80C88 DT/R CPU DEN ALE 1 GND GND AD0-AD7 C1 ADDR/DATA V CC A8-A19 20 GND ...
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NWAIT) = TCY T1 T2 CLK ALE S2-S0 ADDR A19-A16 STATUS ADDR BUS RESERVED ADDR DATA A7-A0 FOR DATA IN RD, INTA READY WAIT DT/R DEN MEMORY ACCESS TIME WP TABLE CHARACTERISTICS 0 0 ...
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Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The 80C88 uses a full 16-bit address on its lower 16 ...
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To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction. INTR may be removed anytime after the falling ...
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READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again three-state its bus drivers transceiver (82C86/82C87) ...
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DT/R, IO/M and SS0 provide the complete bus status in minimum mode. • IO/M has been inverted to be compatible with the 8085 bus structure. • ALE is delayed by one clock cycle in the minimum mode when entering ...
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Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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AC Electrical Specifications SYMBOL PARAMETER MINIMUM COMPLEXITY SYSTEM Timing Requirements (1) TCLCL CLK Cycle Period (2) TCLCH CLK Low Time (3) TCHCL CLK High Time (4) TCH1CH2 CLK Rise Time (5) TCL2CL1 CLK FaIl Time (6) TDVCL ...
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AC Electrical Specifications SYMBOL PARAMETER (33) TCLRL RD Active Delay (34) TCLRH RD Inactive Delay (35) TRHAV RD Inactive to Next Address Active (36) TCLHAV HLDA Valid Delay (37) TRLRH RD Width (38) TWLWH WR Width (39) ...
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Waveforms CLK (82C84A OUTPUT) (30) TCHCTV IO/M, SSO A15-A8 A19/S6-A16/S3 (23) TCLLH ALE RDY (82C84A INPUT) SEE NOTE 9, 10 READY (80C88 INPUT) AD7-AD0 RD READ CYCLE (WR, INTA = DT/R DEN NOTES: 9. RDY is sampled ...
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Waveforms (Continued) CLK (82C84A OUTPUT) TCLAV AD7-AD0 DEN WRITE CYCLE WR TCLAZ AD7-AD0 DT/R INTA CYCLE (NOTE 11) RD INTA DEN SOFTWARE HALT - AD7-AD0 DEN, RD, TCLAV WR, INTA = V OH ALE IO/M DT/R ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) SYMBOL PARAMETER TIMING REQUIREMENTS TCLCL CLK Cycle Period (1) TCLCH CLK Low Time (2) TCHCL CLK High Time (3) TCH1CH2 CLK Rise Time (4) TCL2CL1 CLK Fall ...
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AC Electrical Specifications MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued) SYMBOL PARAMETER MCE Inactive Delay (Note 13) (32) TCLMCL (33) TCLDV Data Valid Delay (34) TCLDX2 Data Hold Time Control Active Delay (Note 13) (35) TCVNV ...
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Waveforms CLK QS0, QS1 (21) TCHSV S2, S1, S0 (EXCEPT HALT) A15-A8 (23) TCLAV A19/S6-A16/S3 TSVLH (27) ALE (82C88 OUTPUT) NOTES 18, 19 RDY (82C84 INPUT) READY 80C86 INPUT) READ CYCLE TCLAV AD7-AD0 RD DT/R 82C88 MRDC OR IORC OUTPUTS ...
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Waveforms (Continued) CLK TCHSV (21) S2, S1, S0 (EXCEPT HALT) WRITE CYCLE AD7-AD0 DEN 82C88 OUTPUTS AMWC OR AIOWC SEE NOTES 22, 23 MWTC OR IOWC INTA CYCLE A15-A8 (SEE NOTES 25, 26) (25) TCLAZ AD7-AD0 (28) TSVMCH MCE/PDEN (30) ...
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Waveforms (Continued) CLK TCLGH (44) (1) TCLCL RQ/GT PREVIOUS GRANT AD7-AD0 RD, LOCK A19/S6-A16/S3 S2, S1, S0 FIGURE 13. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY) NOTE: The coprocessor may not drive the busses outside the region shown without risking contention. ...
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Waveforms (Continued) AC Test Circuit OUTPUT FROM DEVICE UNDER TEST NOTE: Includes stay and jig capacitance. Burn-In Circuits GND GND VCL GND GND VCL GND GND GND VCL VCL VCL OPEN OPEN OPEN OPEN GND GND F0 GND 26 80C88 ...
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Burn-In Circuits (Continued) NOTES: = 5.5V ±0.5V, GND = 0V Input voltage limits (except clock): V (Maximum (Minimum) = 2.6V, V (Clock VCC/2 is external supply set ...
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Die Characteristics METALLIZATION: Type: Silicon - Aluminum ±2k Å Å Thickness: 11K GLASSIVATION: Type: SiO 2 ±1k Å Å Thickness: 8k WORST CASE CURRENT DENSITY 1 A/cm Metallization Mask Layout A11 A10 A9 A8 AD7 AD6 ...
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Instruction Set Summary MNEMONIC AND DESCRIPTION DATA TRANSFER MOV = MOVE: Register/Memory to/from Register Immediate to Regis ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION ARITHMETIC ADD = Add: Register/Memory with Register to Either Immediate to Regis ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Immediate with Accumu lator AAS = ASCll Adjust for ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Immediate Data and Ac cumulator OR = Or: Register/Memory and ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION JMP = Unconditional Jump: Direct Within Segment Direct Within Segment ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION Intersegment Adding Im mediate to SP JE/JZ = Jump ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION CLC = Clear Carry CMC = Complement Car ...
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Instruction Set Summary (Continued) MNEMONIC AND DESCRIPTION NOTES 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to un- signed ...
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Dual-In-Line Plastic Packages (PDIP INDEX N/2 AREA -B- -A- D BASE PLANE -C- SEATING PLANE 0.010 (0.25 NOTES: 1. Controlling Dimensions: INCH. In case of conflict between ...
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Ceramic Dual-In-Line Frit Seal Packages (CERDIP) -A- -D- E -B- bbb BASE Q PLANE -C- SEATING PLANE aaa ccc ...