AD53/009-9 AD [Analog Devices], AD53/009-9 Datasheet

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AD53/009-9

Manufacturer Part Number
AD53/009-9
Description
GSM Baseband Processing Chipset
Manufacturer
AD [Analog Devices]
Datasheet
a
GENERAL DESCRIPTION
The Analog Devices GSM baseband processing chipset provides
a competitive solution for GSM based mobile radio systems. It
is designed to be fully integrated, easy to use, and compatible
with a wide range of product solutions. GSM phones using this
chipset and its accompanying Layer 1, 2, 3 software have passed
the European GSM full type approval process.
The chipset consists of three highly integrated, sub-micron, low
power CMOS components that form the core baseband signal
processing of the GSM handset. The system architecture is
designed to be easily integrated into current designs and form
the basis of next generation of designs.
The chipset uses an operating voltage of 2.7 V to 3.6 V, which
coupled with the extensive power management features,
significantly reduces the drain on battery power and extends the
handset’s talktime and standby time.
CHIPSET COMPONENTS
Algorithm Signal Processor (ASP)
The ASP is an application specific variant of the ADSP-2171
standard DSP from Analog Devices. It has been optimized to
meet the cost, size and power consumption requirements of
GSM mobile applications. All necessary memory to run the
GSM specific programs is provided on-chip and with its
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Passed European GSM Phase I Type Approval
Complete Baseband Processing Chipset Performs:
Embedded 16-Bit Microcontroller
Layer 1 Software Provided with Chipset
Full Phase 2 Protocol Stack Software Available
Integrated SIM- and Keyboard Interface
Ultralow Power Design
JTAG-Boundary Scan
Full Reference Design Available
Three TQFP Devices, Occupying Less than 12 cm
APPLICATIONS
GSM/DCS1800 Mobile Radios and PCMCIA Cards
Speech Coding/Decoding, According to GSM 06.XX
DTMF and Call Progress Tone Generation
Equalization with 16-State Viterbi, Soft Decision
Channel Coding/Decoding According to GSM 05.03
All ADC and DAC Interface Functions
Includes all Radio, Auxiliary and Voice Interfaces
Support for GSM Data Services
2.7 V Operating Voltage
Intelligent Power Management Features
Up to 70 Hours Standby Time Achievable
2
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
preprogrammed ROM, no user programming is required. The
ASP implements full rate speech transcoding according to GSM
specifications, including Discontinuous Transmission (DTX)
and Comfort Noise Insertion (CNI). A high performance soft-
decision Viterbi equalizer is also implemented in software,
embedded in the ROM.
Physical Layer Processor (PLP)
The PLP combines application specific hardware and an
embedded 16-bit microcontroller (Hitachi H8/300H) to
perform channel coding and decoding and execute the protocol
stack and user software. The embedded processor executes the
Layer 1, 2, 3 and user MMI software. The PLP can control all
powerdown functions of the other chips and memory support
components to achieve maximum power savings.
Baseband Converter (BBC)
The BBC performs the voiceband and baseband analog-to-
digital and digital-to-analog conversions, interfacing the digital
sections of the chipset to the microphone, loudspeaker and radio
section. In addition, the BBC contains all the auxiliary convert-
ers for burst-ramping, AFC, AGC, battery and temperature
monitoring. The chipset interfaces directly with a variety of
industry standard radio architectures and supplies all the
synthesizer and timing control signals.
Baseband Processing Chipset
GSM CHIPSET
AD20msp410
512K x 16
PROCESSOR
ALGORITHM
ROM
SIGNAL
ASP
128K x 8
RAM
SYSTEM ARCHITECTURE
PROCESSOR
PHYSICAL
LAYER
PLP
µC
DISPLAY
AD20msp410
CONVERTER
BASEBAND
EEPROM
2K x 8
BBC
© Analog Devices, Inc., 1996
KEYPAD
Fax: 617/326-8703
SUBSYSTEM
RADIO
GSM
SIM

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AD53/009-9 Summary of contents

Page 1

FEATURES Passed European GSM Phase I Type Approval Complete Baseband Processing Chipset Performs: Speech Coding/Decoding, According to GSM 06.XX DTMF and Call Progress Tone Generation Equalization with 16-State Viterbi, Soft Decision Channel Coding/Decoding According to GSM 05.03 All ADC ...

Page 2

AD20msp410 Software The required Layer 1 software is supplied with the chipset. In addition, an object code license for Layers 2 and 3 of the protocol stack is available. This exact package of Layers 1,2,3 of software, coupled with the ...

Page 3

Once these decoding functions are complete, digitized voice data is trans- ferred to the ASP through a parallel port. Error control mecha- nisms are used to ensure adequate bad frame indication. Speech Decoding ...

Page 4

AD20msp410 Automatic Frequency Control (AFC) The mobile radio has to track precisely the master clock provided by the base station. Drift of the crystal oscillator over time and temperature has to be compensated as well as fre- quency shifts due ...

Page 5

Full engineering and test mode support • Support for all phase 1 and phase 2 handover modes • SIM Interface driver • Message interfacing to Layer 3 (Radio Resources Manager) and Layer 2 (data link layer, both signaling and ...

Page 6

AD20msp410 Digital Audio Interface (DAI) As required by the GSM specifications, a digital audio interface is provided to allow certain tests of the audio section during type approval. This interface is provided by the serial bus between the ASP and ...

Page 7

... To order the parts for the AD20msp410 GSM chipset, please order one of each of the following components. Part Part Number ASP ADSP-2178-780244 BBC AD53/009-9 (Special AD7015) +2 3.6 V PLP ADPLP01 An evaluation and development system may be ordered for this chipset, under the part number, AD20msp410-EB03. BBC Unit ...

Page 8

AD20msp410 –8– REV. 0 ...

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