RM5231-250-Q PMC [PMC-Sierra, Inc], RM5231-250-Q Datasheet
RM5231-250-Q
Related parts for RM5231-250-Q
RM5231-250-Q Summary of contents
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... RM5231™ Microprocessor with 32-Bit Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet RM5231 System Bus Data Sheet Issue 1, March 2001 Released ...
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... Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 2 ...
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... Revision History Issue No. Issue Date 1 March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet ECN Number Originator Details of Change 3287 T. Chapman Applied PMC-Sierra template to existing MPD (QED) FrameMaker document ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 4 ...
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... Handshake Signals ......................................................................................................22 3.25 Non-overlapping System Interface ...............................................................................22 3.26 Enhanced Write Modes ................................................................................................23 3.27 External Requests ........................................................................................................24 3.28 Interrupt Handling ........................................................................................................24 3.29 Standby Mode ..............................................................................................................24 3.30 JTAG Interface .............................................................................................................24 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 5 ...
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... Timing Diagrams ...................................................................................................................35 10.1 System Interface Timing ..............................................................................................35 11 Packaging Information ..........................................................................................................36 12 RM5231 128-pin PQFP Package Pinout ...............................................................................38 13 Ordering Information .............................................................................................................39 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 6 ...
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... Figure 7 Processor Block Read .................................................................................................23 Figure 8 Processor Block Write .................................................................................................23 Figure 9 Clock Timing ................................................................................................................35 Figure 10 Input Timing ...............................................................................................................35 Figure 11 Output Timing ............................................................................................................35 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 7 ...
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... Table 5 System Interface ...........................................................................................................26 Table 6 Clock/Control Interface .................................................................................................27 Table 7 Interrupt Interface .........................................................................................................27 Table 8 JTAG Interface .............................................................................................................27 Table 9 Initialization Interface ....................................................................................................28 Table 10 Power Supply .............................................................................................................28 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-Bit System Bus Data Sheet Released 8 ...
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... Standby reduced power mode with WAIT instruction • • 2.5 V core with 3.3 V I/O • 128-pin Power-Quad 4 (QFP) package Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Released 9 ...
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... Register File Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet DTag ITag DTLB ITLB Pad Buffer Address Buffer ...
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... In addition to the integer pipeline, the RM5231 uses an extended 7-stage pipeline for floating-point operations. Figure 3 shows the RM5231 integer pipeline. As illustrated in the figure five integer instructions can be executing simultaneously. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ ...
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... ALU The RM5231 ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder performs address calculations in addition to arithmetic operations. The logic unit performs all logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle ...
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... Hi and Lo registers. These values can then be transferred to the general purpose register file using the Move-from-Hi and Move-from-Lo ( MFHI / MFLO ) instructions. In addition to the baseline MIPS IV integer multiply instructions, the RM5231 also implements the 3 operand multiply instruction, MUL . This instruction specifies that the multiply result go directly to the integer register file rather than the Lo register ...
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... Note: Numbers are represented as single/double precision format. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Latency Repeat Rate 4/5 1/2 4/5 ...
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... In addition, the RM5231 includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection ...
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... This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM5231 provides a single, uniform virtual address space of 1TB ( 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling over 2 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5231 provides a random replacement algorithm to select a TLB entry to be written with a new mapping. However, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism allows the operating system to guarantee that certain pages are always mapped for performance reasons and for deadlock avoidance ...
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... The non-coherent protocols are used for both code and data on the RM5231, with data using write- back or write-through depending on the application. The coherency attributes generate coherent transaction types on the system interface. However, in the RM5231 cache coherency is not supported, hence the coherency attributes should never be used. ...
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... Data Cache For fast, single cycle data access, the RM5231 includes on-chip data cache that is two- way set associative with a fixed 32-byte (eight words) line size. The data cache is protected with byte parity and its tag is protected with a single parity bit virtually indexed and physically tagged to allow simultaneous address translation and data cache access ...
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... In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. The RM5231 cache attributes for both the instruction and data caches are summarized in Table 3. Table 3 Cache Attributes Characteristics ...
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... MB/sec with a 100 MHz SysClock. Figure 6 shows a typical embedded system using the RM5231. In this example, a bank of DRAMs and a memory controller ASIC share the processor’s SysAD bus while the memory controller provides separate ports to a boot ROM and an I/O system ...
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... Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5231 whether it can accept a new read or write transaction. The RM5231 samples these signals before deasserting the address on read and write requests ...
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... Release* 3.26 Enhanced Write Modes The RM5231 implements two enhancements to the original R4000 write mechanism: Write Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus only once every four SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were wait states ...
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... RM5231. An independent transfer is a data transfer between two external agents or between an external agent and memory or peripheral on the system interface. Following the asserting of the ExtRqst*, the RM5231 tri-states its drivers allowing the external agent to use the system interface buses to complete an independent transfer. The external agent is responsible for returning mastership of the system interface to the RM5231 when it has completed the independent transfer and does so by executing an External Null cycle ...
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... Enable the timer interrupt on Int5* 1: Disable the timer interrupt on Int5* 12 Reserved: Must be zero Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Mode bit Description 14:13 Output driver strength - 100% = fastest ...
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... Pin Descriptions The following is a list of interface, interrupt, and miscellaneous pins available on the RM5231. Table 5 System Interface Pin Name Type ExtRqst* Input Release* Output RdRdy* Input WrRdy* Input ValidIn* Input ValidOut* Output SysAD[31:0] Input/Output SysADC[3:0] Input/Output SysCmd[8:0] Input/Output SysCmdP Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ ...
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... JTMS Input Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Description System Clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM5231 that the 3.3V power supply has been above 3.0V for more than 100 milliseconds and will remain stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet 1 Limits 2 – ...
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... VccP must be connected to VccInt through a passive filter circuit. See the RM5200 User’s Manual for the recommended filter circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Vss VccInt VccIO ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Conditions Maximum 0 100 A OUT 0 OUT 0.8 V VccIO + 0 ...
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... Worst case instruction mix with maximum supply voltage. 3. I/O supply power is application dependant, but typically <20% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet CPU Speed 150 MHz 200 MHz 1 ...
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... ModeClock Period JTAG Clock Period Note 1. Operation of the RM5231 is only guaranteed with the Phase Lock Loop enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet CPU Speed 150– ...
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... Only mode 14: tested and guaranteed. 9.4 Boot-Time Interface Parameters Parameter Mode Data Setup Mode Data Hold Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet 1 Conditions 5 mode14.. (fastest) 5 mode14.. mode14 ...
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... SysClock Data Figure 11 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet t t High Low ±t JitterIn (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) ...
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... REF. E3 21.0 REF. L 0.65 0.70 e 0.80 BSC b 0.30 — Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet 2.00 DIA 4 PLACES D1/2 DA-B H 0.20 4X E/2 (E2 E1/2 “COUNTRY OF ORIGIN” MARK 3.00 REF. DIA. 4 PLACES ...
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... JEDEC. 13 defined as the distance from the seating plane to the lowest point of the package body. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Max Note 0.40 ...
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... JTDI 61 30 JTCK 62 31 JTMS 63 32 VccIO 64 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet Function Pin Function ModeIn 65 NMI* RdRdy* 66 ExtRqst* WrRdy* 67 Reset* ValidIn* ...
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... RM5231–200–Q RM5231–250–Q RM5231–200–QI (Contact Sales prior to design) Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002165, Issue 1 RM5231™ Microprocessor with 32-bit System Bus Data Sheet -123 A I Temperature Grade: ...