RM5231A-300-H PMC [PMC-Sierra, Inc], RM5231A-300-H Datasheet
RM5231A-300-H
Related parts for RM5231A-300-H
RM5231A-300-H Summary of contents
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... RM5231A™ Microprocessor with 32-Bit Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet RM5231A System Bus Data Sheet Preliminary Issue 2, September 2001 ...
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... Fax: (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 2 ...
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... March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Details of Change Changed recommended operating conditions VccInt to 1. 1.85 V and VccP to 1. 1.85 V. Added VssP commercial and industrial values. ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. All instruction names, such as MFHI, are in san serif typeface. • Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 4 ...
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... Handshake Signals ......................................................................................................23 3.25 Non-overlapping System Interface ...............................................................................23 3.26 Enhanced Write Modes ................................................................................................24 3.27 External Requests ........................................................................................................25 3.28 Interrupt Handling ........................................................................................................25 3.29 Standby Mode ..............................................................................................................25 3.30 JTAG Interface .............................................................................................................25 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 5 ...
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... RM5231A 128 QFP Package Numerical Pinout ...................................................................38 13 RM5231A 128 QFP Package Alphabetical Pinout ................................................................39 14 Ordering Information .............................................................................................................40 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 6 ...
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... Figure 7 Processor Block Read .................................................................................................24 Figure 8 Processor Block Write .................................................................................................24 Figure 9 Clock Timing ................................................................................................................36 Figure 10 Input Timing ...............................................................................................................36 Figure 11 Output Timing ............................................................................................................36 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 7 ...
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... Table 5 System Interface ...........................................................................................................27 Table 6 Clock/Control Interface .................................................................................................28 Table 7 Interrupt Interface .........................................................................................................28 Table 8 JTAG Interface .............................................................................................................28 Table 9 Initialization Interface ....................................................................................................29 Table 10 Power Supply .............................................................................................................29 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 8 ...
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... Standby reduced power mode with WAIT instruction • • 1. 1.8 V core with 3 2.5 V I/O • 128-pin QFP package Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 9 ...
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... Register File Packer/Unpacker Floating-Point MultAdd, Add, Sub, Cvt, Div, Sqrt Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet DTag ITag DTLB ITLB Pad Buffer Address Buffer ...
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... In addition to the integer pipeline, the RM5231A uses an extended 7-stage pipeline for floating-point operations. Figure 3 shows the RM5231A integer pipeline. As illustrated in the figure five integer instructions can be executing simultaneously. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ ...
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... ALU The RM5231A ALU consists of an integer adder/subtractor, a logic unit, and a shifter. The adder performs address calculations in addition to arithmetic operations. The logic unit performs all logical and zero shift data moves. The shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle ...
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... MUL instruction eliminates the necessity of executing an explicit MFLO instruction. Also included in the RM5231A are the multiply-add instructions, MADU / MAD . This instruction multiplies two operands and adds the resulting product to the current contents of the Hi and Lo registers ...
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... Table 2 gives the latencies of the floating-point instructions in internal processor cycles. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Preliminary 14 ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Latency Repeat Rate 4 ...
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... In addition, the RM5231A includes registers to implement a real-time cycle counting facility to aid in cache diagnostic testing and to assist in data error detection ...
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... This mechanism is available to system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In the user mode, the RM5231A provides a single, uniform virtual address space of 1TB ( 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling over 2 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM5231A provides a random replacement algorithm to select a TLB entry to be written with a new mapping. However, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism uses the Wired register to ‘ ...
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... The non-coherent protocols are used for both code and data on the RM5231A, with data using write-back or write-through depending on the application. The coherency attributes generate coherent transaction types on the system interface. However, in the RM5231A cache coherency is not supported, hence the coherency attributes should never be used. ...
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... The RM5231A supports instruction cache locking. The contents of one set of the cache, set A, can be locked by setting a bit in the coprocessor 0 Status register. Locking the set prevents its contents from being overwritten by a subsequent cache miss. A refill occurs only into set B. This mechanism allows the programmer to lock critical code into the cache thereby guaranteeing deterministic behavior for the locked code sequence ...
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... In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred. The RM5231A cache attributes for both the instruction and data caches are summarized in Table 3. Table 3 Cache Attributes Characteristics ...
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... System Address/Data Bus The 32-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM5231A and the rest of the system protected with a 4-bit parity check bus (SysADC). The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are six handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are used by an external device to indicate to the RM5231A whether it can accept a new read or write transaction. The RM5231A samples these signals before deasserting the address on read and write requests ...
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... Release* 3.26 Enhanced Write Modes The RM5231A implements two enhancements to the original R4000 write mechanism: Write Reissue and Pipeline Writes. The original R4000 allowed a write address cycle on the SysAD bus only once every four SysClock cycles. Hence for a non-block write, this meant that two out of every four cycles were wait states ...
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... Standby Mode The RM5231A provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the WAIT instruction enables interrupts causes the processor to enter Standby Mode. ...
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... Output driver strength - 100% = fastest 00: 67% strength 01: 50% strength 10: 100% strength 11: 83% strength Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Mode bit Description 15 Reserved: Must be zero 17:16 System configuration identifiers - software visible in Config[21 ...
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... Pin Descriptions The following is a list of interface, interrupt, and miscellaneous pins available on the RM5231A. An ‘*’ at the end of the signal name denotes an active low signal. Table 5 System Interface Pin Name Type ExtRqst* Input Release* Output RdRdy* Input WrRdy* Input ValidIn* Input ...
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... JTMS Input Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Description System Clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock. Pipeline operation frequency is derived by multiplying this clock up by the factor selected during boot initialization ...
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... Allows the system to change the processor addressing mode without rewriting the mode ROM. Vcc is OK When asserted, this signal indicates to the RM5231A that both power supplies has been above the recommended value for more than 100 milliseconds and remains stable. The assertion of VccOK initiates the reading of the boot-time mode control serial stream ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet 1 should not exceed 3.9 Volts. IN > ...
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... See the RM5200 User’s Manual for the recommended filter circuit. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Vss VccInt VccIO ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Minimum Maximum 0.2 V VccIO - 0.2 V 0.4 V 2.4 V -0.3 V 0.8 V 2.0 V VccIO + 0 Minimum Maximum ...
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... Dhrystone 2.1 instruction mix. 3. VccIO supply power is application dependant, but typically <20% of VccInt. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet CPU Speed 5% 250 MHz 300 MHz 350 MHz 1 ...
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... JTAG Clock t JTAGCKP Period Note 1. Operation of the RM5231A is only guaranteed with the Phase Lock Loop enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Symbol Min C — ...
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... Mode Data Setup t DS Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet 1 CPU Speed 250 MHz to 350 MHz Min 5,6 1.0 mode14.. ...
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... SysClock Data Figure 11 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet t t High Low ±t JitterIn (SysAD, SysCmd, ValidIn*, ValidOut*, etc.) ...
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... Pin numbers start with Pin #1 and continue counter clockwise to pin #128 when viewed from the top. Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet 0.20 (0.008 A–B ...
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... Vss 27 ModeClock 28 JTDO 29 JTDI 30 JTCK 31 JTMS 32 VccIO Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Pin Function Pin Function 33 ModeIn 65 NMI* 34 RdRdy* 66 ExtRqst* 35 WrRdy* 67 Reset* ...
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... NMI* 65 RdRdy* 34 Release* 38 Reset* 67 SysAD0 117 Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet Function Pin Function SysAD1 118 SysADC1 SysAD2 121 SysADC2 SysAD3 122 ...
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... RM5231A–300–H RM5231A–350–H RM5231A–300–HI (contact sales prior to design) Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use Document ID: PMC-2002174, Issue 2 RM5231A™ Microprocessor with 32-Bit System Bus Data Sheet H I Temperature Grade: (blank) = commercial ...