S29GL-P_12 SPANSION [SPANSION], S29GL-P_12 Datasheet
S29GL-P_12
Related parts for S29GL-P_12
S29GL-P_12 Summary of contents
Page 1
... S29GL-P MirrorBit S29GL01GP, S29GL512P, S29GL256P, S29GL128P 1 Gigabit, 512 Megabit, 256 Megabit and 128 Megabit 3.0 Volt-only Page Mode Flash Memory featuring 90 nm MirrorBit Process Technology Data Sheet Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change ...
Page 2
... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO ® S29GL-P MirrorBit Flash Family S29GL-P_00_A14 October 22, 2012 ...
Page 3
... Uniform 64 Kword/128 Kbyte Sector Architecture – S29GL01GP: One thousand twenty-four sectors – S29GL512P: Five hundred twelve sectors – S29GL256P: Two hundred fifty-six sectors – S29GL128P: One hundred twenty-eight sectors 100,000 erase cycles per sector typical 20-year data retention typical Publication Number S29GL-P_00 This document states the current technical specifications regarding the Spansion product(s) described herein ...
Page 4
... Effective Write Buffer Programming (V ) Per Word HH Sector Erase Time (64 Kword Sector) ® S29GL-P MirrorBit Flash Family CE# Access Time OE# Access Time ( PACC 100/110 110 100 25 110 120 110 25 120 130 µA 60 µs 15 µs 13.5 µs 0.5 s S29GL-P_00_A14 October 22, 2012 ( ...
Page 5
... Customer Lockable Secured Silicon Sector 10.3 Secured Silicon Sector Entry/Exit Command Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 11. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.2 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.3 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.4 Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 11.5 Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 11.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 11.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 October 22, 2012 S29GL-P_00_A14 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 IO ® S29GL-P MirrorBit Flash Family 5 ...
Page 6
... Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 12.1 Command Definitions 12.2 Common Flash Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 13. Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing 14. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ® S29GL-P MirrorBit Flash Family S29GL-P_00_A14 October 22, 2012 ...
Page 7
... Figures Figure 3.1 S29GL-P Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Figure 4.1 64-ball Fortified Ball Grid Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 4.2 LAA064—64ball Fortified Ball Grid Array (FBGA .14 Figure 4.3 56-pin Standard TSOP (Top View Figure 4.4 56-Pin Thin Small Outline Package (TSOP .16 Figure 7.1 Single Word Program Figure 7.2 Write Buffer Programming Operation ...
Page 8
... Table 10.2 Secured Silicon Sector Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Table 10.3 Secured Silicon Sector Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 10.4 Secured Silicon Sector Exit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Table 11.1 Test Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Table 11.2 S29GL-P DC Characteristics (CMOS Compatible .56 Table 11.3 S29GL-P Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Table 11.4 Hardware Reset (RESET .59 Table 11.5 Power-up Sequence Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Table 11.6 S29GL-P Erase and Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Table 11 ...
Page 9
... S29GL01GP DEVICE NUMBER/DESCRIPTION S29GL01GP, S29GL512P, S29GL256P, S29GL128P 3.0 Volt-only, 1024, 512, 256 and 128 Megabit Page-Mode Flash Memory, manufactured MirrorBit October 22, 2012 S29GL-P_00_A14 PACKING TYPE 0 = Tray (standard (Note 5 7” Tape and Reel 3 = 13” Tape and Reel ...
Page 10
... Model Number Packing Type I, C R1 R1 R1 R1 R1 R1 V1, V2 S29GL-P_00_A14 October 22, 2012 ( ...
Page 11
... NC No Connect RY/BY# Output BYTE# Input RESET# Input WP#/ACC Input October 22, 2012 S29GL-P_00_A14 Table 2.1 Input/Output Descriptions Description Address lines for GL01GP A24–A0 for GL512P A23–A0 for GL256P, A22–A0 for GL128P. Data input/output. DQ15: Data input/output in word mode. ...
Page 12
... Physical Dimensions/Connection Diagrams This section shows the I/O designations and package specifications for the S29GL-P family. 4.1 Related Documents The following documents contain information relating to the S29GL-P devices. Click on the title www.spansion.com Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits 4.2 Special Handling Instructions for BGA Package Special handling is required for Flash Memory products in BGA packages ...
Page 13
... A13 WE# A4 RY/BY October 22, 2012 S29GL-P_00_A14 Figure 4.1 64-ball Fortified Ball Grid Array Top View, Balls Facing Down A22 A23 A12 A14 A15 A16 BYTE A10 ...
Page 14
... WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN BALL PITCH - D DIRECTION THE OUTER ROW e/2 BALL PITCH - E DIRECTION 8. NOT USED. SOLDER BALL PLACEMENT 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED DEPOPULATED SOLDER BALLS BALLS. ® S29GL-P MirrorBit Flash Family 3354 \ 16-038.12d S29GL-P_00_A14 October 22, 2012 ...
Page 15
... A18 18 A17 October 22, 2012 S29GL-P_00_A14 Figure 4.3 56-pin Standard TSOP (Top View) ® S29GL-P MirrorBit Flash Family NC on S29GL128P NC on S29GL256P NC on S29GL512P 56 A24 55 A25 54 A16 53 BYTE ...
Page 16
... THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10 mm AND 0.25 mm FROM THE LEAD TIP. 7 LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED FROM THE SEATING PLANE. 8 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. ® S29GL-P MirrorBit Flash Family 3160\38.10A S29GL-P_00_A14 October 22, 2012 ...
Page 17
... Flash Memory Write Buffer Programming and Page Buffer Read Taking Advantage of Page Mode Read on the MCF5407 Coldfire Migration to S29GL128N and S29GL256N based on 110nm MirrorBit Optimizing Program/Erase Times Practical Guide to Endurance and Data Retention Configuring FPGAs using Spansion S29GL-N Flash ...
Page 18
... Product Overview The S29GL-P family consists of 1 Gb, 512 Mb, 256 Mb and 128 Mb, 3.0-volt-only, page mode Flash devices optimized for today’s embedded designs that demand a large storage array and rich functionality. These devices are manufactured using 90 nm MirrorBit technology. These products offer uniform 64 Kword (128 Kbyte) uniform sectors and feature VersatileIO control, allowing control and I/O signals to operate from 1 ...
Page 19
... All sectors are unprotected when shipped from the factory (The Secured Silicon Sector can be factory protected depending on version ordered required by command sequence, data polling, or sector protect algorithm. IN OUT October 22, 2012 S29GL-P_00_A14 Table 6.4 S29GL128P Sector & Memory Address Map Sector Sector Count Range Address Range (16-bit) SA00 0000000h - 000FFFFh 128 : ...
Page 20
... Data is output on DQ15-DQ0 pins after the access time (t IL access time has been meet. ACC or t and subsequent page read accesses (as long as the ACC CE ® S29GL-P MirrorBit Flash Family range is 1. See Ordering has OE . When CE# is de- PACC Fast page mode accesses ACC CE S29GL-P_00_A14 October 22, 2012 ...
Page 21
... Table 7.4 been set as required, the programming equipment may then read the corresponding identifier code on DQ15-DQ0. The Autoselect codes can also be accessed in-system through the command register. October 22, 2012 S29GL-P_00_A14 Table 7.3). The Autoselect codes can also be accessed Table 7 ...
Page 22
... Base + 0Eh 2222h/22h (GL256P) 2221h/21h (GL128P) Device ID, Word 3 Base + 0Fh 2201h/01h For S29GLxxxPH: XX19h/19h = Not Factory Locked. XX99h/99h = Factory Locked. Secure Device Verify Base + 03h For S29GLxxxPL: XX09h/09h = Not Factory Locked. XX89h/89h = Factory Locked. Sector Protect Verify (SA) + 02h xx01h/01h = Locked, xx00h/00h = Unlocked ...
Page 23
... Autoselect exit */ *( (UINT16 *)base_addr + 0x000 ) = 0x00F0; /* exit autoselect (write reset command) */ October 22, 2012 S29GL-P_00_A14 Table 7.4 Autoselect Entry in System (LLD Function = lld_AutoselectEntryCmd) Operation ...
Page 24
... Figure 7.1 for the flowchart. on page 36 for information on these status bits. ® S29GL-P MirrorBit Flash Family and OE when providing address for details on the Unlock Bypass Table 12.1 S29GL-P_00_A14 October 22, 2012 ...
Page 25
... PASS. Device is in October 22, 2012 S29GL-P_00_A14 Figure 7.1 Single Word Program Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Write Program Command: Address 555h, Data A0h Program Data to Address: PA, PD Perform Polling Algorithm (see Write Operation Status ...
Page 26
... MAX ® S29GL-P MirrorBit Flash Family Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 00A0h Word Address Data */ */ */ */ S29GL-P_00_A14 October 22, 2012 ...
Page 27
... Use of the write buffer is strongly recommended for programming when multiple words are to be programmed. October 22, 2012 S29GL-P_00_A14 ® S29GL-P MirrorBit ...
Page 28
... S29GL-P MirrorBit Flash Family Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Sector Address 0025h Sector Address Word Count (N–1)h Word N Sector Address 0029h */ */ */ */ */ */ */ */ */ */ */ */ */ */ */ S29GL-P_00_A14 October 22, 2012 ...
Page 29
... Write Next Word, Decrement wc – 1 RESET. Issue Write Buffer Abort Reset Command October 22, 2012 S29GL-P_00_A14 Figure 7.2 Write Buffer Programming Operation Write Unlock Cycles: Address 555h, Data AAh Address 2AAh, Data 55h Issue Write Buffer Load Command: ...
Page 30
... During the time-out SEA Section 7.7.8 for details on the Unlock Bypass Section 11.7.5 for parameters and timing Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0080h Base + 555h 00AAh Base + 2AAh 0055h Sector Address 0030h */ */ */ */ S29GL-P_00_A14 October 22, 2012 and ...
Page 31
... Yes PASS. Device returns to reading array. Notes 1. See Table 12.1 on page 69 for erase command sequence. 2. See DQ3: Sector Erase Timeout State Indicator October 22, 2012 S29GL-P_00_A14 Figure 7.3 Sector Erase Operation Unlock Cycle 1 Unlock Cycle 2 Command Cycle 1 Command Cycle 2 Command Cycle 3 Specify first sector for erasure • ...
Page 32
... S29GL-P MirrorBit Flash Family 69. These commands invoke the on page 68 Section 7.7.8 for details on the Unlock Bypass Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0080h Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0010h */ */ */ */ S29GL-P_00_A14 October 22, 2012 ...
Page 33
... Level Driver User’s Guide (available on www.spansion.com) for general information on Spansion Flash memory software development guidelines. /* Example: Erase resume command */ *( (UINT16 *)sector_addr ) = 0x0030; /* The flash needs adequate time in the resume state */ October 22, 2012 S29GL-P_00_A14 Table 7.35 for information on these status bits. ...
Page 34
... Table 7.13 Program Resume (LLD Function = lld_ProgramResumeCmd) Operation Byte Address Write Base + XXXh /* write resume command ® S29GL-P MirrorBit Flash Family on page 21 for more information. Word Address Data Base + XXXh 00B0h */ Word Address Data Base + XXXh 0030h */ S29GL-P_00_A14 October 22, 2012 ...
Page 35
... Once you enter Unlock Bypass Mode series of like /* operations (programming or sector erase) and then exit /* Unlock Bypass Mode before beginning a different type of /* operations. October 22, 2012 S29GL-P_00_A14 this input, the device automatically enters the aforementioned Unlock Bypass ...
Page 36
... Table 7.16 Unlock Bypass Reset (LLD Function = lld_UnlockBypassResetCmd) Operation Byte Address Write Base + XXXh Write Base + XXXh ® S29GL-P MirrorBit Flash Family Word Address Data Base + XXXh 00A0h Program Address Program Data */ */ Word Address Data Base + XXXh 0090h Base + XXXh 0000h S29GL-P_00_A14 October 22, 2012 ...
Page 37
... YES NO WriteBuffer program and Read_1 DQ1 is set NO Read_1 DQ5 is set October 22, 2012 S29GL-P_00_A14 Table 7.17, shows the outputs for Data# Polling on DQ7. Figure 11.7, shows the Data# Polling timing diagram. Figure 7.4 Write Operation Status Flowchart - DQ 6 toggles when programming ...
Page 38
... If not all selected sectors are protected, the on page 36). Figure 7.4, Figure 11.13 on page Figure 11.14 on page 64 for additional information. on page ® S29GL-P MirrorBit Flash Family μ s after the program 64, and Table 7.17. Table 7.17 to compare 39 is, the system should then Figure 7.4 S29GL-P_00_A14 October 22, 2012 for ...
Page 39
... DQ1 indicates whether a Write to Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the “Write to Buffer Abort Reset” command sequence to return the device to reading array data. See Write Buffer Programming October 22, 2012 S29GL-P_00_A14 SEA for more details ...
Page 40
... Flash Family DQ5 DQ2 (Note 1) DQ3 (Note 2) DQ1 0 N/A No toggle Toggle N/A Invalid (not allowed) Data 0 N/A Toggle N/A Data 0 N/A N/A N/A 0 N/A N N/A N/A 1 and OE when providing RESET# is held but not at CC5 IL Figure 11.7 S29GL-P_00_A14 October 22, 2012 RY/ BY ...
Page 41
... Abort Reset” command sequence to RESET the device to reading array data. The standard RESET command does not work during this condition. To exit the unlock bypass mode, the system must issue a two-cycle unlock bypass reset command sequence [see Command Definitions October 22, 2012 S29GL-P_00_A14 Table 12.1 on page Table 7 ...
Page 42
... Dynamic Protection Bit 6,7,8 (DYB) DYB 0 DYB 1 DYB 2 DYB N-2 DYB N-1 DYB Sector Protected Sector Unprotected. 8. Protect effective only if PPB Lock Bit is unlocked and corresponding PPB is “1” (unprotected). 9. Volatile Bits: defaults to user choice upon power-up (see ordering options). S29GL-P_00_A14 October 22, 2012 ...
Page 43
... The specific sector address (A25-A16 GL01GP, A24-A16 GL512P, A23-A16 GL256P, A22-A16 GL128P) are written at the same time as the program command the PPB Lock Bit is set, the PPB Program or erase command does not execute and times-out without programming or erasing the PPB. October 22, 2012 S29GL-P_00_A14 Table 8.1 Lock Register ...
Page 44
... Addr = SA0 No DQ6 = Toggle? Yes No DQ5 = 1? Wait 500 µs Yes Read Byte Twice Addr = SA0 No DQ6 = Read Byte. Toggle? Addr = SA Yes No DQ0 = '0' (Pgm.)? FAIL Issue Reset PASS Command Exit PPB Command Set ® S29GL-P MirrorBit Flash Family Figure 8.2. Yes S29GL-P_00_A14 October 22, 2012 ...
Page 45
... The password is all “1”s when shipped from the factory. 4. All 64-bit password combinations are valid as a password. October 22, 2012 S29GL-P_00_A14 they do when ACC =V HH ® ...
Page 46
... The programming of the DYB, PPB, and PPB Lock for a given sector can be verified by writing individual status read commands DYB Status, PPB Status, and PPB Lock Status to the device ® S29GL-P MirrorBit Flash Family S29GL-P_00_A14 October 22, 2012 ...
Page 47
... Write Operation Status Yes PASS. Write Lock Register Exit Command: Address XXXh, Data 90h Address XXXh, Data 00h Device returns to reading array. October 22, 2012 S29GL-P_00_A14 Figure 8.3 Lock Register Program Algorithm Unlock Cycle 1 Unlock Cycle 2 Write XXXh = Address don’t care ...
Page 48
... Sector DYB 0 = protected 1 = unprotected Sector Protection Status x Protected through PPB x Protected through PPB 1 Unprotected 0 Protected through DYB x Protected through PPB x Protected through PPB 0 Protected through DYB 1 Unprotected Figure 8.1 42. . The system must provide the LKO is greater than LKO S29GL-P_00_A14 October 22, 2012 for CC ...
Page 49
... Flash memory. 9.4 Output Disable (OE#) When the OE# input impedance state. (With the exception of RY/BY#.) October 22, 2012 S29GL-P_00_A14 and OE during power up, the device does not accept commands on the ...
Page 50
... Spansion factory with the Secured Silicon Sector permanently locked. Contact your local representative for details on using Spansion programming services Table 10.1 Secured Silicon Sector Addresses Customer Lockable ESN Factory Locked ESN Determined by customer Unavailable ® S29GL-P MirrorBit Flash Family ExpressFlash Factory Locked ESN or determined by customer Determined by customer S29GL-P_00_A14 October 22, 2012 ...
Page 51
... Entry Cycle Note Base = Base Address. /* Example: SecSi Sector Entry Command */ *( (UINT16 *)base_addr + 0x555 ) = 0x00AA; *( (UINT16 *)base_addr + 0x2AA ) = 0x0055; *( (UINT16 *)base_addr + 0x555 ) = 0x0088; October 22, 2012 S29GL-P_00_A14 page 68 [Secured Silicon Sector Command Table, Appendix through Table 12.4 on page 72 for address and data requirements for both command Table 10 ...
Page 52
... SecSi Sector Exit cycle 4 */ ® S29GL-P MirrorBit Flash Family Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 00A0h Word Address Data Word Word Address Data Base + 555h 00AAh Base + 2AAh 0055h Base + 555h 0090h Base + XXXh 0000h */ */ S29GL-P_00_A14 October 22, 2012 ...
Page 53
... Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. October 22, 2012 S29GL-P_00_A14 ...
Page 54
... S29GL-P MirrorBit Flash Family Range –40°C to +85°C 0°C to +85° +1. The I/Os do not operate when All Speeds 30 5 0.0–V IO 0. Outputs Steady S29GL-P_00_A14 October 22, 2012 Unit ...
Page 55
... IO 0.5 V Input IO 0.0 V Note If V < the input measurement reference level is 0 October 22, 2012 S29GL-P_00_A14 Inputs Don’t Care, Any Change Permitted Does Not Apply Figure 11.4 Input Waveforms and Measurement Levels Measurement Level . IO ® S29GL-P MirrorBit ...
Page 56
... DC Characteristics Table 11.2 S29GL-P DC Characteristics (CMOS Compatible) Parameter Parameter Description Symbol (Notes) I Input Load Current Input Load Current LIT I Output Leakage Current Active Read Current (1) CC1 Non-Active Output IO2 Intra-Page Read Current CC2 CC V Active Erase CC3 ...
Page 57
... Figure 11.3 and Table 11.1 for test specifications. 5. Unless otherwise indicated, AC specifications for 110 ns speed options are tested with V with V = 1.8 V and October 22, 2012 S29GL-P_00_A14 Table 11.3 S29GL-P Read Operations Test Setup 2 1. ...
Page 58
... CE HIGH Z and t are specific to a read cycle following a flash write operation. CEH OEH Figure 11.6 Page Read Timings Same Page Aa t PACC t ACC Qa ® S29GL-P MirrorBit Flash Family HIGH Z Output Valid PACC PACC S29GL-P_00_A14 October 22, 2012 ...
Page 59
... S29GL-P Hardware Reset (RESET#) Operation Parameter JEDEC Std. RESET# Pin Low (During Embedded Algorithms Ready Read Mode or Write mode RESET# Pin Low (NOT During Embedded Algorithms) t Ready to Read Mode or Write mode t RESET# Pulse Width RP t Reset High Time Before Read ...
Page 60
... Table 11.5 Power-up Sequence Timings Description (or last Reset pulse (or last Reset pulse VCS VIOS ) is 20 mA. IL Figure 11.8 Power-up Sequence Timings min min t VIOS t VCS ® S29GL-P MirrorBit Flash Family Speed Unit Min 35 µs Min 35 µs Min 200 S29GL-P_00_A14 October 22, 2012 ...
Page 61
... S29GL-P Erase and Program Operations Table 11.6 S29GL-P Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ASO t t Address Hold Time ...
Page 62
... Figure 11.9 Program Operation Timings WPH A0h t BUSY is the true data at the program address. OUT ® S29GL-P MirrorBit Flash Family Read Status Data (last two cycles WHWH1 D Status OUT VHH S29GL-P_00_A14 October 22, 2012 ...
Page 63
... VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle for data polling when V = 1.65 to 2.7 V and when CE# does not need to go high between status bit reads October 22, 2012 S29GL-P_00_A14 555h for chip erase ...
Page 64
... Valid Valid Status Status (first read) (second read) Figure 11.14 DQ2 vs. DQ6 Enter Erase Suspend Program Erase Erase Suspend Suspend Read Program ® S29GL-P MirrorBit Flash Family Valid Valid Data Status (stops toggling) Erase Resume Erase Erase Complete Read S29GL-P_00_A14 October 22, 2012 ...
Page 65
... S29GL-P Alternate CE# Controlled Erase and Program Operations Table 11.7 S29GL-P Alternate CE# Controlled Erase and Program Operations Parameter Description JEDEC Std. (Notes Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# low during toggle bit polling ...
Page 66
... Data# Polling GHEL t t WHWH1 CPH t BUSY for program PD for program 55 for erase 30 for sector erase 10 for chip erase is the data written to the device. OUT ® S29GL-P MirrorBit Flash Family PA DQ7# D OUT S29GL-P_00_A14 October 22, 2012 ...
Page 67
... TSOP Pin and BGA Package Capacitance Parameter Symbol OUT C IN2 WP#/ACC RESET# CE# Notes 1. Sampled, not 100% tested. 2. Test conditions T = 25° 100 MHz. A October 22, 2012 S29GL-P_00_A14 Typ Max (Note 1) (Note 2) 0.5 3.5 64 256 128 512 256 1024 512 ...
Page 68
... A reset command is then required to return the device to reading array data Section 5. define the valid register command sequences. Writing incorrect address and ® S29GL-P MirrorBit Flash Family For the latest information, explore S29GL-P_00_A14 October 22, 2012 ...
Page 69
... Table 12.1 S29GL-P Memory Array Command Definitions, x16 Command (Notes) Read (6) 1 Reset (7) 1 Manufacturer ID 4 Device ID (8) 6 Sector Protect Verify (10) 4 Secure Device Verify (11) 4 CFI Query (12) 1 Program 4 Write to Buffer (13) 6 Program Buffer to Flash (Confirm) 1 Write-to-Buffer-Abort Reset (14) 3 Enter ...
Page 70
... Table 12.2 S29GL-P Sector Protection Command Definitions, x16 Command (Notes) Command Set Entry 3 Program (6) 2 Read (6) 1 Command Set Exit ( Command Set Entry 3 Password Program (9) 2 Password Read (10) 4 Password Unlock (10) 7 Command Set Exit ( PPB Command Set Entry 3 PPB Program (11, 12) ...
Page 71
... Table 12.3 S29GL-P Memory Array Command Definitions, x8 Command (Notes) Read (6) 1 Reset (7) 1 Manufacturer ID 4 Device ID (8) 6 Sector Protect Verify (10) 4 Secure Device Verify (11) 4 CFI Query (12) 1 Program 4 Write to Buffer (13) 6 Program Buffer to Flash (confirm) 1 Write-to-Buffer-Abort Reset (14) 3 Enter 3 Program ...
Page 72
... Table 12.4 S29GL-P Sector Protection Command Definitions, x8 Command (Notes) Command Set Entry 3 Bits Program (6) 2 Read (6) 1 Command Set Exit ( Command Set Entry 3 Password Program (9) 2 Password Read (10) 8 Password Unlock (10) 11 Command Set Exit ( PPB Command Set Entry 3 PPB Program (11, 12) ...
Page 73
... Addresses (x16) 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah October 22, 2012 S29GL-P_00_A14 write CFI entry command */ /* write cfi exit command Table 12.5 CFI Query Identification String (x8) Data 20h 0051h 22h 0052h Query Unique ASCII string “QRY” ...
Page 74
... Erase Block Region 4 Information (refer to CFI publication 100) 0000h 0000h ® S29GL-P MirrorBit Flash Family Description pin present) PP pin present µs N µs (00h = not supported (00h = not supported) N times typical N times typical N times typical N times typical (00h = not supported) Description N S29GL-P_00_A14 October 22, 2012 ...
Page 75
... A0h October 22, 2012 S29GL-P_00_A14 Data 0050h 0052h Query-unique ASCII string “PRI” 0049h 0031h Major version number, ASCII 0033h Minor version number, ASCII Address Sensitive Unlock (Bits 1-0) ...
Page 76
... Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Warm Reset Timing At power on, the flash requires additional time in the reset state to self configure than it does during a warm reset. Table 13.1 and the GL-P, and GL-S flash. Parameter t VCS t VIOS t RPH CEH t RPH t RP ...
Page 77
... GL-P so designs that have CE# fixed low cannot migrate to GL-S without modification to enable active CE# control. The GL-S allows V IO During power ramp no input is allowed to exceed V power management and control to design a robust and reliable system. October 22, 2012 S29GL-P_00_A14 Figure 13.2 Warm Reset Timing RPH. after V ...
Page 78
... Max. Read Access Times table: Added note. Hardware Reset Deleted note from section. AC Characteristics Reset Timings figure: Deleted note. S29GL-P Sector Protection Command Definitions tables: Changed “Global Non-Volatile Freeze” to Command Definitions tables “Global Volatile Freeze”. DC Characteristics CMOS Compatible table: Changed I Page Read Timings figure Corrected address range for top waveform ...
Page 79
... Chip Program Time: removed comment Sector Protection Command Definition, Corrected Lock Register “Read” address x16 Table Advance Information on S29GL MirrorBit Hardware Reset (RESET#) Power-Up Sequence Timings Table: modified Note 2 - reduced timing from 500 µs to 300 µs and Power-up Sequence ...
Page 80
... Corrected Address for 3rd Cycle of Write-To-Buffer-Abort Reset command Command Definitions, x8 Table System Interface String Changed value of address 20h (x16) to 0006h Updated section title to Advance Information on S29GL-S Eclipse 65 nm MirrorBit Power-On and Advance Information on S29GL-R Warm Reset Timing 65 nm MirrorBit Hardware Reset ...
Page 81
... Copyright © 2004–2012 Spansion Inc. All rights reserved. Spansion combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. October 22, 2012 S29GL-P_00_A14 ® ...