LTC3735 LINER [Linear Technology], LTC3735 Datasheet - Page 19

• Manufacturer Part Number: LTC3735
• Description: 2-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs
• Manufacturer: LINER [Linear Technology]

APPLICATIONS INFORMATION
After the output voltage enters the ±10% regulation window
centered at V
issues a logic high signal. Refer to the timing diagram in
Figure 7. This signal then enters a logic AND gate, with
MCH_PG being the other input, and the output of the gate
is PG shown in Figure 7. This composite PG signal is then
delayed by t
As soon as MD is asserted, the output voltage changes
from V
the six VID bits. In the LTC3735, the time t
be 15 switching cycles:
If f
If f
(=(INTERNAL PG)
AND (MCH_PG))
COMPOSITE PG
COMPARATOR)
POWER GOOD
INTERNAL PG
S
S
t
(OUTPUT OF
BOOT
is set at 210kHz, t
is set at 550kHz, t
INTERNAL
MCH_PG
VID BITS
RUN/SS
BOOT
V
OUT
MD
= 15
BOOT
to V
Figure 7. Start-Up Timing Diagram
BOOT
f
1
S
VID
amount of time and then becomes MD.
, the internal power good comparator
, a voltage level totally controlled by
INVALID
1.5V
BOOT
BOOT
V
BOOT
90% V
= 71µs
= 27µs
BOOT
t
TIME
BOOT
BOOT
V
VALID
VID
is set to
3735 F07
Output Voltage Set in Deep Sleep and Deeper Sleep
States (Refer to the Functional Diagram)
The output voltage can be offset by the STP_CPUB signal.
When STP_CPUB becomes low, the output voltage will be
a certain percentage lower than that set by the VID bits in
Table 2. This state is defined to be the deep sleep state.
Referring to the Functional Diagram, we can caluculate
the STP_CPUB offset to be:
By using different R4 resistors, STP_CPUB offset can be
programmed.
The output voltage could also be set by external resistors
R6 and R4 when DPRSLPVR input is high. This state is
defined to be the deeper sleep state. The output voltage
is set to V
By using different value R6 resistors, V
programmed.
(The digital input threshold voltage is set to 1.8V for
STP_CPUB, DPRSLPVR and MCH_PG inputs.)
Power Good Masking
The PGOOD output monitors V
within ±10% of the set point, PGOOD is pulled low with
an internal MOSFET. When V
window, PGOOD is high impedance. PGOOD should be
pulled up by an external resistor.
During VID changes, deep sleep and deeper sleep transi-
tions, the output voltage can initially be out of the ±10%
window of the newly set regulation point. To avoid nui-
sance indications from PGOOD, a timer masks PGOOD for
110µs. If V
time, PGOOD goes low. Any overvoltage or undervoltage
condition is also masked for 110µs before it is reported
by PGOOD.
STP% = –
V
DPRSLPVR
DPRSLPVR
OUT
R3 +R4
= 0.6V •
is still out of regulation after this blanking
R3
, regardless of the VID setting:
• 100%
(
R2 • R3 +R6||R4
R6||R4
(
OUT
)
OUT
• R1+R2
is within the regulation
(
. When V
LTC3735
DPRSLPVR
)
)
OUT
19
can be
is not
3735fa