S29GL032A10BAIR12 SPANSION [SPANSION], S29GL032A10BAIR12 Datasheet - Page 24

• Manufacturer Part Number: S29GL032A10BAIR12
• Description: 64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
• Manufacturer: SPANSION [SPANSION]

22
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
automatic sleep mode current specification.
The automatic sleep mode minimizes Flash device energy consumption. The de-
vice automatically enables this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-
trol signals. Standard address access timings provide new data when addresses
are changed. While in sleep mode, output data is latched and always available to
the system. Refer to the
The RESET# pin provides a hardware method of resetting the device to reading
array data. When the RESET# pin is driven low for at least a period of t
device immediately terminates any operation in progress, tristates all output
pins, and ignores all read/write commands for the duration of the RESET# pulse.
The device also resets the internal state machine to reading array data. The op-
eration that was interrupted should be reinitiated once the device is ready to
accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held
at V
at V
The RESET# pin may be tied to the system reset circuitry. A system reset would
thus also reset the Flash memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# parameters and to
for the timing diagram.
When the OE# input is at V
are placed in the high impedance state.
IL
SS
±0.3 V, the device draws CMOS standby current (I
but not within V
SS
S29GLxxxA MirrorBit™ Flash Family
±0.3 V, the standby current will be greater.
IH
A d v a n c e
“DC Characteristics” section on page 65
, output from the device is disabled. The output pins
I n f o r m a t i o n
CC5
). If RESET# is held
Figure 15
S29GLxxxA_00_A2 January 28, 2005
for the
RP
ACC
, the
+