S29GL032A10BAIR12 SPANSION [SPANSION], S29GL032A10BAIR12 Datasheet - Page 40

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S29GL032A10BAIR12

Manufacturer Part Number
S29GL032A10BAIR12
Description
64 MEGABIT 32MEGABIT 3.0 BOLT ONLY PAGE MODE FLASH MEMORY
Manufacturer
SPANSION [SPANSION]
Datasheet
A d v a n c e
I n f o r m a t i o n
mode. Subsequent writes are ignored until V
is greater than V
. The system
CC
LKO
must provide the proper signals to the control pins to prevent unintentional writes
when V
is greater than V
.
CC
LKO
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#, CE# or WE# do not initiate a write
cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# = V
, CE# = V
or WE# =
IL
IH
V
. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a
IH
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
and OE# = V
during power up, the device does not accept
IL
IH
commands on the rising edge of WE#. The internal state machine is automatically
reset to the read mode on power-up.
38
S29GLxxxA MirrorBit™ Flash Family
S29GLxxxA_00_A2 January 28, 2005

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