LTC3786 LINER [Linear Technology], LTC3786 Datasheet - Page 10

• Manufacturer Part Number: LTC3786
• Description: Multi-Phase Current Mode Step-Up DC/DC Controller
• Manufacturer: LINER [Linear Technology]

pin FuncTions
LTC3862-2
3V8: Output of the Internal 3.8V LDO from INTV
pin for the low voltage analog and digital circuits. A low
ESR 1nF ceramic bypass capacitor should be connected
between 3V8 and SGND, as close as possible to the IC.
BLANK: Blanking Time. Floating this pin provides a nominal
minimum on-time of 290ns. Connecting this pin to 3V8
provides a minimum on-time of 375ns, while connecting
it to SGND provides a minimum on-time of 210ns.
CLKOUT: Digital Output Used for Daisy-Chaining Multiple
LTC3862-2 ICs in Multi-Phase Systems. The PHASEMODE
pin voltage controls the relationship between CH1 and CH2
as well as between CH1 and CLKOUT.
D
maximum duty cycle. Floating this pin provides 84%
duty cycle. Connecting this pin to 3V8 provides 75% duty
cycle, while connecting it to SGND provides 96% duty
cycle. The maximum duty cycle limit is derived from an
internal clock that runs at 12× the programmed switching
frequency. As a result, the maximum duty cycle limit D
is extremely precise.
FB: Error Amplifier Input. The FB pin should be connected
through a resistive divider network to V
output voltage.
FREQ: A resistor from FREQ to SGND sets the operating
frequency.
GATE1, GATE2: Gate Drive Output. The LTC3862-2 pro-
vides a 10V gate drive referenced to PGND to drive a high
voltage MOSFET.
10
MAX
: Maximum Duty Cycle. This pin programs the
OUT
CC
to set the
. Supply
MAX
INTV
(LDO). A low ESR 4.7µF (X5R or better) ceramic bypass
capacitor should be connected between INTV
as close as possible to the IC.
ITH: Error Amplifier Output. The current comparator trip
threshold increases with the ITH control voltage. The ITH
pin is also used for compensating the control loop of the
converter.
PGND: Power Ground. Connect this pin close to the sources
of the power MOSFETs. PGND should also be connected to
the negative terminals of V
tors. PGND is electrically isolated from the SGND pin. The
exposed pad of the QFN and FE packages is connected to
PGND and must be soldered to PCB ground for electrical
contact and rated thermal performance.
PHASEMODE: The PHASEMODE pin voltage programs
the phase relationship between CH1 and CH2 rising gate
signals, as well as the phase relationship between CH1
gate signal and CLKOUT. Floating this pin or connecting
it to either 3V8, or SGND changes the phase relationship
between CH1, CH2 and CLKOUT.
PLLFLTR: PLL Lowpass Filter Input. When synchronizing
to an external clock, this pin serves as the lowpass filter
input for the PLL. A series resistor and capacitor connected
from PLLFLTR to SGND compensate the PLL feedback loop.
RUN: Run Control Input. A voltage above 1.22V on the pin
turns on the IC. Forcing the pin below 1.22V causes the
IC to shut down. There is a 0.5µA pull-up current for this
pin. Once the RUN pin raises above 1.22V, an additional
4.5µA pull-up current is added to the pin for program-
mable hysteresis.
CC
: Output of the Internal 10V Low Dropout Regulator
IN
and INTV
CC
bypass capaci-
CC
and PGND,
38622f