SC16C754 Philips Semiconductors, SC16C754 Datasheet
SC16C754
Available stocks
Related parts for SC16C754
SC16C754 Summary of contents
Page 1
... The SC16C754 is a quad universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs, automatic hardware/software flow control, and data rates Mbits/s (3.3 V and 5 V). The SC16C754 offers enhanced features. It has a transmission control register (TCR) that stores receiver FIFO threshold levels to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets the status of TXRDY/RXRDY for all four ports in one access ...
Page 2
... Product data 8-bit characters Even, odd parity bit generation and detection 1, 1. stop bit generation Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Version 12 1.4 mm SOT315-1 SOT188-2 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 3
... CONTROL LOGIC MODEM CONTROL LOGIC CLOCK AND BAUD RATE GENERATOR XTAL1 XTAL2 CLKSEL Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO TXA-TXD RXA-RXD DTRA-DTRD RTSA-RTSD CTSA-CTSD RIA-RID CDA-CDD DSRA-DSRD 002aaa206 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 4
... TXB 12 CSB 13 INTB 14 RTSB 15 GND 16 DTRB 17 CTSB 18 DSRB Fig 2. LQFP80 pin configuration. 9397 750 11618 Product data SC16C754IB80 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO DSRD 58 CTSD 57 DTRD 56 GND 55 RTSD 54 INTD 53 CSD 52 TXD 51 IOR 50 TXC ...
Page 5
... UART channels A through D. A logic LOW on these pins indicates that a carrier has been detected by the modem for that channel. The state of these inputs is reflected in the modem status register (MSR). Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 60 DSRD ...
Page 6
... Clear to Send (Active-LOW). These inputs are associated with individual UART channels A through D. A logic 0 (LOW) on the CTS pins indicates the modem or data set is ready to accept transmit data from the SC16C754. Status can be tested by reading MSR[4]. These pins only affect the transmit and receive operations when Auto-CTS function is enabled via the Enhanced Feature Register EFR[7] for hardware fl ...
Page 7
... Enhanced Feature Register (EFR[6]) for hardware flow control operation. I Receive data input. These inputs are associated with individual serial channel data to the SC16C754. During the local loop-back mode, these RX input pins are disabled and TX data is connected to the UART RX input internally. O Receive Ready (Active-LOW) ...
Page 8
... The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the SC16C754 UART can be read at any time during functional operation by the processor. The SC16C754 can be placed in an alternate mode (FIFO mode) relieving the processor of excessive software overhead by buffering received/transmitted characters ...
Page 9
... RTS CTS FLOW CONTROL PARALLEL TO-SERIAL CTS RTS FLOW CONTROL 3). Figure 5 shows RTS functional timing. The receiver FIFO Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO UART 2 PARALLEL- TO-SERIAL TX FIFO FLOW CONTROL D7-D0 SERIAL-TO- PARALLEL RX FIFO FLOW CONTROL 002aaa228 Figure 1 “ ...
Page 10
... X X transmit Xon1, Xoff1 transmit Xon2, Xoff2 transmit Xon1, Xon2, Xoff1, Xoff2 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO START N N+1 002aaa226 Section 6.2.1. START BYTE 0-7 STOP 002aaa227 Table 3 shows software flow © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 11
... Xoff interrupt is cleared by a read of the IIR. The special character is transferred to the RX FIFO. 6.3.1 RX When software flow control operation is enabled, the SC16C754 will compare incoming data with Xoff1,2 programmed characters (in certain cases, Xoff1 and Xoff2 must be received sequentially). When the correct Xoff character are received, transmission is halted after completing transmission of the current character ...
Page 12
... COMPARE Xoff-2 WORD PROGRAMMED Xon-Xoff CHARACTERS UART1 is transmitting a large text file to UART2. Both UARTs are summarizes the state of register after reset. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO UART2 RECEIVE FIFO DATA SERIAL-TO-PARALLEL PARALLEL-TO-SERIAL Xon-1 WORD ...
Page 13
... Signal RESET functions Reset control RESET RESET RESET RESET RESET Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Reset state All bits cleared. Bit 0 is set. All other bits cleared. All bits cleared. Reset to 00011101 (1D hex). All bits cleared. ...
Page 14
... Philips Semiconductors 6.5 Interrupts The SC16C754 has interrupt generation and prioritization (six prioritized levels of interrupts) capability. The interrupt enable register (IER) enables each of the six types of interrupts and the INT signal in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0-3, 5-7. When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt through IIR[5 ...
Page 15
... Fig 9. FIFO polled mode operation. 9397 750 11618 Product data Figure 8 shows interrupt mode operation. IOW / IOR INT PROCESSOR IOW / IOR PROCESSOR Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO IIR IER THR RHR 002aaa230 Figure 9 ...
Page 16
... LOCATION FILLED TXRDY FIFO EMPTY When empty, the TXRDY signal becomes active. TXRDY will go inactive RXRDY is active when there is at least one character in the FIFO. It Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO RX RXRDY rdptr AT LEAST ONE LOCATION FILLED ...
Page 17
... It will go inactive when the FIFO is empty or an error in the RX FIFO is flagged by LSR[7]. 6.7 Sleep mode Sleep mode is an enhanced feature of the SC16C754 UART enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set. Sleep mode is entered when: • ...
Page 18
... When a break condition occurs, the TX line is pulled LOW. A break condition is activated by setting LCR[6]. 6.9 Programmable baud rate generator The SC16C754 UART contains a programmable baud generator that takes any clock input and divides divisor in the range between 1 and (2 divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in ...
Page 19
... Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Percent error difference between desired and actual 0.026 0.058 0.69 2.86 Percent error difference between desired and actual 0.026 0.034 0.312 0.628 1.23 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 20
... FIFO ready register Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 1 1.8432 MHz 002aaa169 Write mode transmit holding register (THR) interrupt enable register ...
Page 21
... The Special Register set is accessible only when LCR[7] is set to a logic 1. [4] Enhanced Feature Register; Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF 9397 750 11618 Product data lists and describes the SC16C754 internal registers. Bit 6 Bit 5 Bit 4 bit 6 ...
Page 22
... TX terminal. If the FIFO is disabled, the FIFO is still used to store the byte. Characters are lost if overflow occurs. 9397 750 11618 Product data Table 9 for more register access information. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 23
... FIFO. FCR[0] FIFO enable. Logic 0 = Disable the transmit and receive FIFO (normal default condition). Logic 1 = Enable the transmit and receive FIFO. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 24
... Word length bits 1, 0. These two bits specify the word length to be transmitted or received bits bits bits bits Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 25
... Logic 1 = Overrun error has occurred. LSR[0] Data in receiver. Logic data in receive FIFO (normal default condition). Logic least one character in the RX FIFO. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 26
... RTS output is controlled by hardware flow control. MCR[0] DTR Logic 0 = Force DTR output to inactive (HIGH). Logic 1 = Force DTR output to active (LOW). In loop-back mode, controls MSR[5]. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 27
... Logic 1 = Enable the RTS interrupt. [1] IER[5] Xoff interrupt. Logic 0 = Disable the Xoff interrupt (normal default condition). Logic 1 = Enable the Xoff interrupt. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Table 15 shows modem status © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 28
... IIR[3:1] 3-bit encoded interrupt. See IIR[0] Interrupt status. Logic interrupt is pending. Logic interrupt is pending. Table Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO …continued Section 6.7 “Sleep mode” for details. Table 18. 18. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 29
... MCR[7:5] can be modified, i.e., this bit is therefore a write enable. EFR[3:0] Combinations of software flow control can be selected by programming these bits. See Table 3 “Software flow control options (EFR[0:3])” on page 10. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO IIR[1] IIR[0] Source of the interrupt 1 0 Receiver Line Status error ...
Page 30
... Trigger Level Register bits description Symbol Description TLR[7:4] RX FIFO trigger levels (4-60), number of characters available. TLR[3:0] TX FIFO trigger levels (4-60), number of spaces available. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Table 20 shows transmission © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 31
... There are less than a TX trigger level number of spaces available in the TX FIFO There are at least a TX trigger level number of spaces available in the TX FIFO. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 32
... Set MCR (04 temp3 Set TCR (06) to VALUE Set MCR (04) to temp3 Set LCR (03 Set EFR (02) to temp2 Set LCR (03) to temp1 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 33
... Set prescaler value to divide-by-4 [1] 9397 750 11618 Product data Register programming guide sign here means bit-AND. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO …continued Actions Read LCR (03), save in temp1 Set LCR (03 Read EFR (02), save in temp2 Set EFR (02 temp2 ...
Page 34
... Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 9397 750 11618 Product data Conditions Min - 0.3 0.3 in free-air 40 65 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Max Unit 0 0.3 V ...
Page 35
... V on non-hysteresis inputs. IH(max) Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 3.3 V and 5 V Min Nom Max + 10 ...
Page 36
... Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 3.3 V 5.0 V Unit Max Min Max - MHz - ...
Page 37
... ADDRESS t 13h ACTIVE t 15d t 13w ACTIVE t 16h t 16s DATA t 6h VALID ADDRESS t 7h ACTIVE ACTIVE t 12h t 12d DATA Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 002aaa109 002aaa110 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 38
... Product data t 17d CHANGE OF STATE CHANGE OF STATE t 18d ACTIVE t ACTIVE Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO CHANGE OF STATE t 18d ACTIVE ACTIVE 19d ACTIVE ACTIVE t 18d CHANGE OF STATE © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 002aaa352 ...
Page 39
... DATA BITS 6 DATA BITS 7 DATA BITS 16 BAUD RATE CLOCK DATA BITS (5– Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT 20d ACTIVE t 21d ACTIVE ...
Page 40
... DATA BITS (5– DATA BITS 6 DATA BITS 7 DATA BITS ACTIVE TX READY t 22d 16 BAUD RATE CLOCK Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO PARITY STOP BIT BIT D6 D7 FIRST BYTE THAT REACHES THE TRIGGER LEVEL t 25d ACTIVE DATA ...
Page 41
... Product data DATA BITS (5- ACTIVE TRANSMITTER READY TRANSMITTER NOT READY Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO NEXT DATA PARITY STOP START BIT BIT BIT © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 42
... Product data DATA BITS (5- DATA BITS 6 DATA BITS 7 DATA BITS t 28d FIFO FULL Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO PARITY STOP BIT BIT D6 D7 002aaa365 © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 43
... scale (1) ( 0.18 12.1 12.1 14.15 14.15 0.5 1 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC JEITA MS-026 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO detail (1) ( 0.75 1.45 1.45 7 0.2 0.15 0.1 0.30 1.05 1.05 0 EUROPEAN ISSUE DATE ...
Page 44
... REFERENCES JEDEC JEITA MS-018 EDR-7319 Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO SOT188 detail X (1) ( max ...
Page 45
... Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 11618 Product data 2.5 mm thick/large packages. Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO 3 350 mm so called 3 so called small/thin packages. © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 46
... Suitability of surface mount IC packages for wave and reflow soldering methods [1] [3] , [5] , SO, SOJ Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Soldering method Wave Reflow not suitable suitable [4] not suitable suitable ...
Page 47
... I CCsleep characteristics”: add Table note 2, its reference to parameter ‘IOW Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO : change all values nom. © Koninklijke Philips Electronics N.V. 2003. All rights reserved ...
Page 48
... Rev. 04 — 19 June 2003 SC16C754 Quad UART with 64-byte FIFO Fax: + 24825 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. ...
Page 49
... Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 19 June 2003 Document order number: 9397 750 11618 SC16C754 Quad UART with 64-byte FIFO 9 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 34 10 Static characteristics ...