CY7C1061AV33 Cypress Semiconductor, CY7C1061AV33 Datasheet

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CY7C1061AV33

Manufacturer Part Number
CY7C1061AV33
Description
1M x 16 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet

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0
Cypress Semiconductor Corporation
Document #: 38-05256 Rev. *D
Features
Functional Description
The CY7C1061AV33 is a high-performance CMOS Static
RAM organized as 1,048,576 words by 16 bits.
Writing to the device is accomplished by enabling the chip
(CE
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
• High speed
• Low active power
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
Logic Block Diagram
— t
— 1080 mW (max.)
A
A
A
A
A
A
A
A
A
A
1
0
1
2
3
4
5
6
7
8
9
LOW and CE
AA
= 8, 10, 12 ns
0
through I/O
2
INPUT BUFFER
4096 x 4096
HIGH) while forcing the Write Enable
DECODER
COLUMN
1M x 16
ARRAY
7
), is written into the location
1
and CE
3901 North First Street
2
features
Commercial
Industrial
Commercial/Industrial
I/O
I/O
0
8
–I/O
–I/O
BHE
WE
CE
CE
OE
BLE
specified on the address pins (A
Enable (BHE) is LOW, then data from I/O pins (I/O
I/O
(A
Reading from the device is accomplished by enabling the chip
by taking CE
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins will appear on I/O
High Enable (BHE) is LOW, then data from memory will appear
on I/O
sheet for a complete description of Read and Write modes.
The input/output pins (I/O
high-impedance state when the device is deselected (CE
HIGH/CE
BHE and BLE are disabled (BHE, BLE HIGH), or during a
Write operation (CE
The CY7C1061AV33 is available in a 54-pin TSOP II package
with center power and ground (revolutionary) pinout, and a
48-ball fine-pitch ball grid array (FBGA) package.
2
1
0
7
15
15
through A
) is written into the location specified on the address pins
8
to I/O
2
LOW), the outputs are disabled (OE HIGH), the
San Jose
1
19
15
LOW and CE
).
. See the truth table at the back of this data
300
300
50
-8
8
1
LOW, CE
Pin Configuration
I/O
I/O
I/O
I/O
BHE
CE
1M x 16 Static RAM
V
V
CE
V
I/O
V
I/O
I/O
I/O
WE
V
A
A
A
A
A
CC
CC
SS
A
A
A
A
CC
A
SS
19
18
12
13
14
15
17
16
15
2
4
3
2
1
0
1
0
1
2
3
0
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
1
2
3
4
5
6
7
8
9
10
11
12
CA 95134
2
275
275
-10
through I/O
10
50
TSOP II (Top View)
HIGH while forcing the Output
2
HIGH, and WE LOW).
0
Revised February 21, 2003
through A
54
53
52
50
49
39
38
37
36
35
34
33
32
31
30
29
28
CY7C1061AV33
51
48
47
46
45
44
43
42
41
40
I/O
V
V
I/O
I/O
V
I/O
A
A
A
A
A
NC
V
DNU (Do Not Use)
A
A
A
A
A
V
OE
BLE
I/O
I/O
I/O
I/O
15
SS
SS
260
260
CC
9
SS
10
CC
-12
5
6
7
8
11
12
13
14
12
50
11
9
10
8
7
6
5
4
) are placed in a
19
0
408-943-2600
). If Byte High
to I/O
8
7
Unit
through
mA
mA
. If Byte
ns
1

Related parts for CY7C1061AV33

CY7C1061AV33 Summary of contents

Page 1

... HIGH/CE 2 BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE The CY7C1061AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball fine-pitch ball grid array (FBGA) package. I/O –I/O ...

Page 2

... I BHE I/O I I I/O I/O I I/O I/O DNU CY7C1061AV33 Page ...

Page 3

... IN IL MAX CE <= 0.3V Commercial/ 2 Max Industrial CC CE > V – 0.3V > V – 0.3V < 0.3V Description MHz CY7C1061AV33 [1] ................................ –0. Ambient Temperature +70 C – + -10 Min. Max. Min. Max. Min. Max. 2.4 2.4 2.4 0.4 0.4 2.0 V 2 0.3 + 0.3 –0.3 0.8 – ...

Page 4

... are specified with a load capacitance ( Test Loads. Transition is measured 200 mV from \LZWE LZBE LOW (CE HIGH) and WE LOW. Chip enables must be active and WE and byte enables must 1 2 CY7C1061AV33 R1 317 3. pF* 351 INCLUDING JIG AND SCOPE (b) ...

Page 5

... Over the Operating Range (continued) -8 Min. Max [6] 3 [6] 6 DATA RETENTION MODE 3.0V V > CDR OHA . CE2 = CY7C1061AV33 [4] -10 -12 Min. Max. Min. Max 5 3. DATA VALID Unit ...

Page 6

... RC t ACE t DOE t LZOE t DBE t LZBE 50% [13, 14, 15 SCE PWE t transition LOW and CE transition HIGH and CE combined active LOW CY7C1061AV33 t HZOE t HZCE t HZBE IMPEDANCE DATA VALID HIGH I ICC Page ...

Page 7

... BHE, BLE WE CE DATAI/O Write Cycle No.3 (WE Controlled, OE LOW) ADDRESS BHE, BLE DATA I/O Document #: 38-05256 Rev PWE t SCE t SD [13, 14, 15 SCE PWE HZWE SD CY7C1061AV33 LZWE Page ...

Page 8

... H X Ordering Information Speed [16] (ns) Ordering Code 8 CY7C1061AV33-8ZC CY7C1061AV33-8ZI CY7C1061AV33-8BAC CY7C1061AV33-8BAI 10 CY7C1061AV33-10ZC CY7C1061AV33-10ZI CY7C1061AV33-10BAC CY7C1061AV33-10BAI 12 CY7C1061AV33-12ZC CY7C1061AV33-12ZI CY7C1061AV33-12BAC CY7C1061AV33-12BAI Note: 16. Contact a Cypress representative for availability of the 48-ball Mini BGA (BA48) package. Document #: 38-05256 Rev. *D BHE I/O –I/O I/O –I High-Z High-Z X ...

Page 9

... Package Diagrams Document #: 38-05256 Rev. *D 54-lead Thin Small Outline Package, Type II Z54-II CY7C1061AV33 51-85160-** Page ...

Page 10

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1061AV33 51-85162-*A ...

Page 11

... Document History Page Document Title: CY7C1061AV33 Static RAM Document Number: 38-05256 Issue REV. ECN NO. Date ** 113725 03/28/02 *A 117058 07/31/02 *B 117989 08/30/02 *C 120383 11/06/02 *D 124439 2/25/03 Document #: 38-05256 Rev. *D Orig. of Change Description of Change NSL New Data Sheet DFP Removed 15-ns bin. DFP Added 8-ns bin. Changed Icc for 8, 10, 12 bins. ...

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