CY7C128A Cypress Semiconductor, CY7C128A Datasheet

no-image

CY7C128A

Manufacturer Part Number
CY7C128A
Description
2K x 8 Static RAM
Manufacturer
Cypress Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY7C128A-15DC
Manufacturer:
CYP
Quantity:
2 376
Part Number:
CY7C128A-15DMB
Manufacturer:
CY
Quantity:
5
Part Number:
CY7C128A-15DMB
Manufacturer:
CYP
Quantity:
1 665
Part Number:
CY7C128A-15PC
Manufacturer:
CY
Quantity:
6 238
Part Number:
CY7C128A-15PC
Quantity:
325
Part Number:
CY7C128A-15VC
Manufacturer:
HARRIS
Quantity:
72
Part Number:
CY7C128A-20DC
Manufacturer:
CYP
Quantity:
446
Part Number:
CY7C128A-20DMB
Manufacturer:
CY
Quantity:
11
Part Number:
CY7C128A-20DMB
Manufacturer:
TI
Quantity:
650
Part Number:
CY7C128A-20LMB
Manufacturer:
CY
Quantity:
3
Company:
Part Number:
CY7C128A-20PC
Quantity:
773
Features
Selection Guide
Cypress Semiconductor Corporation
• Automatic power-down when deselected
• CMOS for optimum speed/power
• High speed
• Low active power
• Low standby power
• TTL-compatible inputs and outputs
• Capable of withstanding greater than 2001V electro-
• V
Maximum Access Time (ns)
Maximum Operating
Current (mA)
Maximum Standby
Current (mA)
static discharge
— 15 ns
— 440 mW (commercial)
— 550 mW (military)
— 110 mW
IH
CE
WE
Logic Block Diagram
OE
of 2.2V
A
A
A
A
A
A
A
10
9
8
7
6
5
4
A
3
INPUT BUFFER
128 x 16 x 8
DECODER
COLUMN
ARRAY
A
2
Commercial
Military
Commercial
Military
A
1
A
0
POWER
DOWN
3901 North First Street
7C128A–15
40/40
120
15
Functional Description
The CY7C128A is a high-performance CMOS static RAM or-
ganized as 2048 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), and active LOW
output enable (OE) and three-state drivers. The CY7C128A
has an automatic power-down feature, reducing the power
consumption by 83% when deselected.
Writing to the device is accomplished when the chip enable
(CE) and write enable (WE) inputs are both LOW.
Data on the eight I/O pins (I/O
memory location specified on the address pins (A
A
Reading the device is accomplished by taking chip enable
(CE) and output enable (OE) LOW while write enable (WE) remains
HIGH. Under these conditions, the contents of the memory location
specified on the address pins will appear on the eight I/O pins.
The I/O pins remain in high-impedance state when chip enable
(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.
The CY7C128A utilizes a die coat to insure alpha immunity.
7C128A–20
10
).
C128A–1
40/20
40/20
100
125
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
20
0
1
2
3
4
5
6
7
San Jose
Pin Configurations
7C128A–25
December 1988 – Revised December 1992
100
125
25
20
40
2K x 8 Static RAM
I/O
I/O
GND
I/O
I/O
I/O
A
A
A
A
A
CA 95134
A
A
A
A
A
A
A
A
2
0
4
3
1
0
0
1
7
2
1
0
0
1
2
6
5
4
3
through I/O
7C128A–35
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
DIP/SOJ
Top View
11 12 13 14 15
Top View
3 2 1
7C128A
7C128A
LCC
100
100
35
20
20
24
24
23
22
21
20
19
18
17
16
15
14
13
23
CY7C128A
7
22
21
20
19
18
17
16
) is written into the
WE
V
A
A
OE
A
CE
I/O
I/O
I/O
I/O
I/O
CC
8
9
10
A
WE
OE
A
CE
I/O
I/O
7
6
5
4
3
9
10
C128A–2
408-943-2600
C128A–3
7C128A–45
7
6
0
100
45
20
through

Related parts for CY7C128A

CY7C128A Summary of contents

Page 1

... HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the eight I/O pins. The I/O pins remain in high-impedance state when chip enable (CE) or output enable (OE) is HIGH or write enable (WE) is LOW. The CY7C128A utilizes a die coat to insure alpha immunity. I/O 0 I/O ...

Page 2

... Com’l 120 = 0 mA Mil , Com’ IH, Mil , Com’ –0.3V, CC –0.3V CC Mil < 0.3V Test Conditions MHz 5. CY7C128A Ambient Temperature +70 C – +125 C Min. Max. Min. Max. Min. 2.4 2.4 2.4 0.4 0.4 2.2 V 2 –0.5 0.8 –0.5 0.8 –0.5 –10 +10 – ...

Page 3

... HZCE LZCE 3 CY7C128A ALL INPUT PULSES 3.0V 90% 90% 10% GND 5 ns 7C128A–25 7C128A–35 7C128A–45 Min. Max. Min. Max. Min. Max ...

Page 4

... Data I/O pins enter high-impedance state, as shown, when OE is held LOW during write OHA DOE DATA VALID 50 SCE PWE t SD DATA t HZWE . IL 4 CY7C128A DATA VALID t HZOE t HZCE IMPEDANCE VALID IN t LZWE HIGH IMPEDANCE C128A–6 HIGH ICC ISB C128A–7 C128A–8 ...

Page 5

... CC V =5. 0.0 –55 25 AMBIENT TEMPERATURE( C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE 1.6 1.4 1.2 1.0 V =5.0V CC 0.8 0.6 –55 25 125 AMBIENT TEMPERATURE CY7C128A HIGH IMPEDANCE OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 V =5. = 125 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ...

Page 6

... Ordering Code 15 CY7C128A–15PC CY7C128A–15VC 20 CY7C128A–20PC CY7C128A–20VC CY7C128A–20DMB CY7C128A–20LMB 25 CY7C128A–25PC CY7C128A–25VC CY7C128A–25DMB CY7C128A–25LMB 35 CY7C128A–35PC CY7C128A–35VC CY7C128A–35DMB CY7C128A–35LMB 45 CY7C128A–45DMB CY7C128A–45LMB TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 25.0 20.0 15.0 10.0 V =4. = ...

Page 7

... ACE 10, 11 DOE WRITE CYCLE 10 10, 11 SCE 10, 11 PWE 10 10 Document #: 38–00094–B 7 CY7C128A ...

Page 8

... Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL–STD–1835 D– 9 Config.A 24-Pin Rectangular Leadless Chip Carrier L53 24-Lead (300-Mil) Molded DIP P13/P13A 8 CY7C128A ...

Page 9

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead Molded SOJ V13 CY7C128A ...

Related keywords