SY10EL34L Micrel Semiconductor, SY10EL34L Datasheet

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SY10EL34L

Manufacturer Part Number
SY10EL34L
Description
5V/3.3V /2 /4 /8 CLOCK GENERATION CHIP
Manufacturer
Micrel Semiconductor
Datasheet

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FEATURES
3.3V and 5V power supply options
50ps output-to-output skew
Synchronous enable/disable
Master Reset for synchronization
Internal 75K input pull-down resistors
Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
V
V
Q
Q
Q
Q
Q
Q
CC
CC
0
0
1
1
2
2
1
2
3
4
5
6
7
8
TOP VIEW
Q
Q
Q
R
R
R
SOIC
÷2
÷4
÷8
Q D
R
11
10
16
15
14
13
12
9
V
EN
NC
CLK
CLK
V
MR
V
5V/3.3V 2, 4, 8 CLOCK
GENERATION CHIP
CC
BB
EE
1
generation chips designed explicitly for low skew clock
generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the V
coupled into the device. If a single-ended input is to be
used, the V
input and bypassed to ground via a 0.01 F capacitor.
The V
reference for the input of the EL34/L under single-ended
input conditions. As a result, this pin can only source/
sink up to 0.5mA of current.
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the divider stages. The
internal enable flip-flop is clocked on the falling edge of
the input clock, therefore, all associated specification
limits are referenced to the negative edge of the clock
input.
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34/Ls in a system.
DESCRIPTION
The SY10/100EL34/L are low skew
The common enable (EN) is synchronous so that the
Upon start-up, the internal flip-flops will attain a random
PIN NAMES
CLK
EN
MR
V
Q
Q
Q
BB
Pin
BB
0
1
2
output is designed to act as the switching
BB
BB
output should be connected to the CLK
output, a sinusoidal source can be AC-
Differential Clock Inputs
Synchronous Enable
Master Reset
Reference Output
Differential 2 Outputs
Differential 4 Outputs
Differential 8 Outputs
Function
ClockWorks™
SY100EL34/L
Rev.: F
Issue Date: August, 1998
SY10EL34/L
2,
4,
Amendment: /0
8 clock

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SY10EL34L Summary of contents

Page 1

FEATURES 3.3V and 5V power supply options 50ps output-to-output skew Synchronous enable/disable Master Reset for synchronization Internal 75K input pull-down resistors Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM ÷ ...

Page 2

Micrel TRUTH TABLE CLK NOTE LOW-to-HIGH transition ZZ = HIGH-to-LOW transition DC ELECTRICAL CHARACTERISTICS (Min (Max.); Symbol ...

Page 3

... EN signal not been asserted. PRODUCT ORDERING CODE 3.3V Ordering Package Operating Code Type SY10EL34LZC Z16-2 Commercial SY10EL34LZCTR Z16-2 Commercial SY100EL34LZC Z16-2 Commercial SY100EL34LZCTR Z16-2 Commercial 5V V Range ...

Page 4

Micrel 16 LEAD SOIC .150" WIDE (Z16-2) MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 980-9191 TEL This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use ...

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