IDT71215 Integrated Device Technology, IDT71215 Datasheet

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IDT71215

Manufacturer Part Number
IDT71215
Description
BiCMOS StaticRAM 240K (16K x 15-BIT) CACHE-TAG RAM For the PentiumO Processor
Manufacturer
Integrated Device Technology
Datasheet

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FEATURES:
• 16K x 15 Configuration
• Match output uses Valid bit to qualify MATCH output
• High-Speed Address-to-Match comparison times
• Asynchronous Read/Match operation with Synchronous
• Separate
• Separate
• Synchronous
• Dual Chip selects for easy depth expansion with no
• I/O pins both 5V TTL and 3.3V LVTTL compatible with
• Packaged in a 80-pin Thin Plastic Quad Flat Pack
DESCRIPTION:
organized 16K x 15 and designed to support the Pentium and
other Intel processors at bus speeds up to 66MHz. There are
twelve common I/O TAG bits, with the remaining three bits
used as status bits. A 12-bit comparator is on-chip to allow fast
comparison of the twelve stored TAG bits and the current Tag
input data. An active HIGH MATCH output is generated when
these two groups of data are the same for a given address.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Pentium is a trademark of Intel Corporation
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
1996 Integrated Device Technology, Inc.
– 12 TAG Bits
– 3 Separate I/O Status Bits (Valid, Dirty, Write Through)
– 8/9/10/12ns over commercial temperature range
BRDY
speed operation
Write and Reset operation
performance degredation
V
PWRDN
(TQFP)
Integrated Device Technology, Inc.
The IDT71215 is a 245,760-bit Cache Tag StaticRAM,
A
CS1
WET
WES
OET
OES
RESET
PWRDN
SFUNC
W/
VLD
DTY
WT
CCQ
0
R
– A
IN
, CS2
IN
IN
pins
/ S
circuitry included inside the Cache-Tag for highest
/ S
13
/ S
pin to place device in low-power mode
3IN
1IN
WE
OE
2IN
for the TAG bits, the Status bits, and
for the TAG bits and the Status bits
RESET
Address Inputs
Chip Selects
Write Enable - Tag Bits
Write Enable - Status Bits
Output Enable - Tag Bits
Output Enable - Status Bits
Status Bit Reset
Powerdown Mode Control Pin
Status Bit Function Control Pin
Write/Read Input from Processor
Valid Bit / S
Dirty Bit / S
Write Through Bit / S
pin for invalidation of all Tag entries
2
1
Bit Input
Bit Input
3
Bit Input
BiCMOS StaticRAM
240K (16K x 15-BIT)
CACHE-TAG RAM
For the Pentium Processor
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
BRDY
14.3
This high-speed MATCH signal, with t
provides the fastest possible enabling of secondary cache
accesses.
be configured for either dedicated or generic functionality,
depending on the SFUNC input pin. With SFUNC LOW, the
status bits are defined and used internally by the device,
allowing easier determination of the validity and use of the
given Tag data. SFUNC HIGH releases the defined internal
status bit usage and control, allowing the user to configure the
status bit information to fit his system needs. A synchronous
RESET
all status bits in the array for easy invalidation of all Tag
addresses.
(
MATCH, VLD bit, WT bit, and external inputs provided by the
user. This can significantly simplify cache controller logic and
minimize cache decision time. Match and Read operations
are both asynchronous in order to provide the fastest access
times possible, while Write operations are synchronous for
ease of system timing.
rate V
with both 5.0V TTL and 3.3V LVTTL Logic levels. The
pin offers a low-power standby mode to reduce power con-
sumption by 90%, providing significant system power sav-
ings.
high-reliability BiCMOS technology and is offered in a space-
saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
BRDY
The three separate I/O status bits (VLD, DTY, and WT) can
The IDT71215 also provides the option for Burst Ready
The IDT71215 uses a 5V power supply on Vcc with sepa-
The IDT71215 is fabricated using IDT's high-performance,
CLK
BRDYH
BRDYOE
BRDYIN
BRDY
TAG
VLD
DTY
WT
MATCH
V
V
V
CC
CCQ
SS
CCQ
OUT
) generation within the cache tag itself, based upon
OUT
pin, when held LOW at a rising clock edge, will reset
OUT
0
– TAG
/ S
/ S
pins provided for the outputs to offer compliance
/ S
3OUT
1OUT
2OUT
11
System Clock
BRDY
BRDY
Additional
Burst Ready
Tag Data Input/Outputs
Valid Bit / S
Dirty Bit / S
Write Through Bit / S
Match
+5V Power
Output Buffer Power
Ground
Force High
Output Enable
BRDY
2
1
Bit Output
Bit Output
Input
3
Bit Output
ADM
as fast as 8ns,
AUGUST 1996
IDT71215
Output
Output
Output
Output
Output
PWRDN
QPwr
Input
Input
Input
Input
DSC-3075/3
Gnd
Pwr
1
3075 tbl 01
I/O

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IDT71215 Summary of contents

Page 1

... Match and Read operations are both asynchronous in order to provide the fastest access times possible, while Write operations are synchronous for ease of system timing. The IDT71215 uses a 5V power supply on Vcc with sepa- rate V CCQ with both 5.0V TTL and 3.3V LVTTL Logic levels. The ...

Page 2

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM PIN CONFIGURATION DTY / COMMERCIAL TEMPERATURE RANGE PN80-1 TQFP TOP VIEW 14 TAG8 TAG7 TAG6 VLD / S1 OUT ...

Page 3

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM FUNCTIONAL BLOCK DIAGRAM ADDR (0:13) CS1 CS2 Reg TAG (0:11) OET WRITE (pos) PULSE GENERATOR WET Reg WES CLK RESET (neg) PULSE GENERATOR RESET PWRDN SFUNC W/ R BRDYH BRDYIN Reg BRDYOE 0 Reg MEMORY 1 TAG BITS Data in Register 14.3 COMMERCIAL TEMPERATURE RANGE ...

Page 4

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TRUTH TABLES CHIP SELECT, RESET, AND POWER-DOWN FUNCTIONS CS2 CLK CS1 RESET PWRDN RESET WET WET WES CS1 PWRDN CHIP SELECT FUNCTION RESET FUNCTION ...

Page 5

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TRUTH TABLES (CONT.) ( MATCH FUNCTION CS2 SFUNC CS1 OET WET WES CS1 OET WET WES ...

Page 6

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM RECOMMENDED DC OPERATING CONDITIONS Symbol Parameter Min. V Supply Voltage 4. Output Buffers 4.75 CCQ V 3.3V Output Buffers 3.0 CCQ V Supply Ground Input High Voltage 2 I/O High Voltage 2.2 IHQ V Input Low Voltage –0.5 IL NOTE (min.) = –1.5V for pulse width of less than 10ns, once per cycle. ...

Page 7

... IDT71215S9 IDT71215S10 IDT71215S12 Max. Min. Max. Min. 4 — 4 — — 1 — 1 — 60 — 60 — 2 — 2 — 2 — 10 — 10 — — 120 — ...

Page 8

... IDT71215S8 IDT71215S9 Min. Max. 15 4.5 4 Invalid — BRDY 1.5 — — 0 LOW 5 Active 50 WES 14.3 COMMERCIAL TEMPERATURE RANGE IDT71215S10 IDT71215S12 Min. Max. Min. Max. Min. — 15 — 15 — 16.6 — 4.5 — 4.5 — 5 — 4.5 — 4.5 — 5 — 3 — 3 — 3 — ...

Page 9

... BRDY Valid — 6 BRDY Invalid — 6 Valid — 7 BRDY — 6 — 6 Invalid — 7 BRDY Valid — 8 BRDY 14.3 COMMERCIAL TEMPERATURE RANGE IDT71215S9 IDT71215S10 IDT71215S12 Min. Max. Min. Max. Min. — 9 — 10 — — 9 — 10 — — 9 — 10 — 1 — 1 — ...

Page 10

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Timing Reference Levels AC Test Load AC TEST LOADS V CCQ Outputs 347 Figure 1. AC Test Load Tag I/O and Outputs 347 Figure 3. AC Test Load (for t ...

Page 11

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TIMING WAVEFORMS OF WRITE AND READ CYCLES COMMERCIAL TEMPERATURE RANGE 14.3 11 ...

Page 12

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TIMING WAVEFORMS OF MATCH AND FUNCTIONS BRDY BRDY 14.3 COMMERCIAL TEMPERATURE RANGE 12 ...

Page 13

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TIMING WAVEFORMS OF RESET RESET CLK t SR RESET t PDSR PWRDN VLD OUT DTY OUT WT OUT t S WES WET BRDY MATCH TAG (0:11) NOTE: 1. Transition is measured 200mV from steady state. CLOCK TIMING WAVEFORM t CH CLK 2.0V 2.0V TIMING WAVEFORMS OF BRDY BRDY ...

Page 14

... IDT71215 BiCMOS 16Kx15 CACHE-TAG RAM TIMING WAVEFORMS OF OES OES OES VLD OUT DTY OUT Valid Output WT OUT NOTE: 1. Transition is measured 200mV from steady state. TIMING WAVEFORMS OF POWER DOWN FUNCTION PWRDN t WHPL CLK t RHPL RESET WET WES TAG (0:11) VLD OUT DTY ...

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