HEF40160BD Philips Semiconductors, HEF40160BD Datasheet
HEF40160BD
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HEF40160BD Summary of contents
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DATA SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF40160B MSI 4-bit synchronous decade counter with asynchronous reset Product specification File ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset DESCRIPTION The HEF40160B is a fully synchronous edge-triggered 4-bit decade counter with a clock input (CP), an overriding asynchronous master reset (MR), four parallel data inputs ( three synchronous mode control inputs (parallel 0 3 enable (PE), count enable parallel (CEP) and count enable ...
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Acrobat reader. white to force landscape pages to be ... Fig.2 Logic diagram. ...
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... X = state is immaterial January 1995 PINNING CEP CET HEF40160BP(N): HEF40160BD(F): HEF40160BT(D Package Designator North America TERMINAL COUNT GENERATION MODE CET preset no change no change count Note CET O 4 Product specification HEF40160B parallel enable input parallel data inputs ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset AC CHARACTERISTICS input transition times SS amb V Dynamic power dissipation per 10 package ( CHARACTERISTICS pF; input transition times SS amb Propagation delays HIGH to LOW 10 15 LOW to HIGH ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset V V Output transition times HIGH to LOW 10 15 LOW to HIGH CHARACTERISTICS pF; input transition times SS amb L V Minimum clock pulse width; LOW 10 15 Minimum MR pulse width; LOW 10 15 Recovery time ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset V Maximum clock pulse frequency 10 15 Conditions PE = LOW HIGH 0 3 Fig.5 Waveforms showing minimum CP and MR pulse widths and recovery time. Conditions HIGH. Fig.6 Waveforms showing set-up times and hold times for CEP and CET inputs ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset Conditions PE = LOW MR = HIGH Fig.7 Waveforms showing set-up times and hold times for P Condition MR = HIGH Fig.8 Waveforms showing set-up times and hold times for PE inputs. Note Set-up and hold times are shown as positive values but may be specified as negative values. ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset APPLICATION INFORMATION An example of an application for the HEF40160B is: Programmable decade counter. January 1995 Fig.9 Timing diagram. 9 Product specification HEF40160B MSI ...
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... Philips Semiconductors 4-bit synchronous decade counter with asynchronous reset NOTE On the TC outputs, glitches can occur during counting. In totally synchronous mode they will not have any adverse affect. However the TC output in asynchronous mode can cause problems. January 1995 Fig.10 Synchronous multi-stage counting scheme. ...