DS2165-DS2165Q Dallas Semiconducotr, DS2165-DS2165Q Datasheet
DS2165-DS2165Q
Related parts for DS2165-DS2165Q
DS2165-DS2165Q Summary of contents
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... DESCRIPTION The DS2165Q ADPCM processor chip is a dedicated digital-signal-processing (DSP) chip that has been optimized to perform adaptive-differential pulse-code modulation (ADPCM) speech compression at three different rates. The chip can be programmed to compress (expand) 64kbps voice data down to (up from) either 32kbps, 24kbps, or 16kbps ...
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... Connecting SPS high enables the software mode. In this mode, an external host controller writes configuration data to the DS2165Q by the serial port through inputs SCLK, SDI, and write to the DS2165Q is either a 2-byte write or a 4-byte write. A 2-byte write consists of the address/command byte (ACB), followed by a byte to configure the control register (CR) for either the channel ...
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... Y Frame Sync. 8kHz frame sync for the Y-side PCM interface. Y Data Clock. Data clock for the Y-side PCM interface; must be synchronous with FSY. Y Data In. Sampled on falling edge of CLKY during selected time slots. Positive Supply. 5.0V (3.0V for DS2165QL for normal operation select the serial port; connect to V ...
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... Bypass operates on bytewide (8 bits) slots when CP/ (4 bits) slots when CP/ is cleared and m-law (U/ A-law ( CR.2. If BYP and IPD are cleared, then CP/ expanded PCM coding is independently selected for the X and Y channels A determines if the input data compressed DS2165Q is set and on nibble-wide EX ...
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... Algorithm Reset 0 = normal operation 1 = reset algorithm for selected channel Bypass 0 = normal operation 1 = bypass selected channel Data Format 0 = A-law 1 = m-law Algorithm Select 2 (Table 2) Channel Coding 0 = expand (decode) selected channel 1 = compress (encode) selected channel DS2165Q (LSB (LSB) AS2 U/ A CP/ EX ...
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... LSB of input time slot register FUNCTION Reserved. Must be 0 for proper operation Reserved. Must be 0 for proper operation MSB of output time slot register — — — — LSB of output time slot register AS0 DS2165Q (LSB) D0 (LSB) D0 ...
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... Note: Time slots are counted from the frame sync signal starting at the first rising edge of either CLKX or CLKY after the frame sync. Figure 7. m-LAW PCM INTERFACE Figure 8. m-LAW ADPCM INTERFACE and U/ (Figures 7 through 10). For and it is set to expect m-law data DS2165Q . The number EX ...
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... Figure 9. A-LAW PCM INTERFACE Figure 10. A-LAW ADPCM INTERFACE DS2165Q ...
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... Channel X Coding Configuration 0 = Expand 1 = Compress Algorithm Select (Table 4) Channel X Data Format 0 = A-law 1 = m-law Channel Y Coding Configuration 0 = Expand 1 = Compress Algorithm Select (Table 4) Channel Y Data Format 0 = A-law 1 = m-law Channel Y Idle Select 0 = Channel Active 1 = Channel Idle Channel X Idle Select 0 = Channel Active 1 = Channel Idle DS2165Q ...
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... Hold A1 and A4 low during a hardware reset; take both A1 and A4 high after the 64kpbs to/from 24kbps has returned high (allow 3ms after returns high before taking A1 and A4 high). 64kbps to/from 16kbps Connect both A1 and Figure 11. DS2165Q CONNECTION TO CODEC/FILTER * Suggested Codec/Filters TP305X National Semiconductor ETC505X STMicroelectronics MC1455XX Motorola, Inc ...
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... Figure 12. PCM AND ADPCM I/O EXAMPLE Note 1: The bit after the LSB in the 24kbps ADPCM output is only a 1 when the DS2165Q is operated in the software mode and is programmed to perform 24kbps compression; in all other configurations ...
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... INPUT TO OUTPUT DELAY With all three compressions algorithms, the total delay, from the time the PCM data sample is captured by the DS2165Q to the time it is output, is always less than 375ms. The exact delay is determined by the input and output time slots selected for each channel. ...
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... +0 +0 TYP MAX UNITS ±10 0°C to +70° 3.0V + 20% - 10% for DS2165QL) TYP MAX UNITS +1 DS2165Q NOTES +25°C) NOTES NOTES ...
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... IL = 0°C to +70° SYMBOL MIN WMH 45 t WML RST 3.0V + 20% - 10% for DS2165QL) DD TYP MAX UNITS 3906 150 ns 150 ns = 3.0V + 20% - 10% for DS2165QL) DD TYP ...
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... CDH t 250 CL t 250 250 CCH t 250 CWH t 50 SCC = 0.8V, and 10ns maximum rise and fall times 3.0V + 20% - 10% for DS2165QL) DD TYP MAX UNITS 100 DS2165Q NOTES ...
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... Figure 13. PCM INTERFACE AC TIMING DIAGRAM Figure 14. MASTER CLOCK/RESET AC TIMING DIAGRAM Figure 15. SERIAL PORT AC TIMING DIAGRAM Note: SCLK can be either high or low when CS is taken low DS2165Q ...
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... PLCC INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 — B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 D 0.485 0.495 D1 0.450 0.456 D2 0.390 0.430 E 0.485 0.495 E1 0.450 0.456 E2 0.390 0.430 L1 0.060 — — e1 0.050 BSC CH1 0.042 0.048 DS2165Q ...