MC146818A Motorola, MC146818A Datasheet
MC146818A
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MC146818A Summary of contents
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... I Advance Information I REAL-TIME CLOCK PLUS RAM (RTC) The MC146818A Real-Time Clock plus RAM is a peripheral device which includes the unique MOTEL concept microprocessors, microcomputers, combines three unique features: alarm and one hundred year calendar, a programmable rupt and square-wave generator, RAM. The MC146818A uses high-speed CMOS technology to interface with 1 MHz processor buses, while consuming very little power ...
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... Current ~rai~~r Pin Excluding Vmi,a%q,.vs s Op&~~~&Temperature Range ‘~%$~6818A TA ‘<@c146818AC Storage Temperature Range Tstg THERMAL CHARACTERISTICS Characteristic Thermal Resistance Plastic Cerdlp Ceramic MOTOROLA @ FIGURE 1 – BLOCK DIAGRAM v VSS) to Value Unit v –0.3 to +8.0 V5S– O.5 to VDD+O – ...
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ELECTRICAL CHARACTERISTICS ( Characteristics Frequency of Operation Output Voltage lLoad< lOpA IDD – Bus Idle CKOUT=fosc, CL= 15 pF; SOW Disabled, STBY=O.2 fosc=32.76B kHz IDD – Quiescent fosc= DC; OSC1 = DC; All Other V; lnpUtS=vDD–0.2 ...
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... Hold Time after AS/ALE Fall 33 NOTE: Designations E, ALE, ~, and ~R refer to signals from alternative * Refer to IMPORTANT NOTICES appearing V, VLOW=O.8 Note: VHIGH=VDD–2.O VHIGH=2.O V, VLOW=O.5 V, for VDD=3.O MOTOROLA @ Vnn=3.O ti;F Load Symbol Min Max 5000 tcvc High PWEL lm Low PWEH 15m — tr, tf tRWH ...
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... C= (Chip Select) STBY ADO-AD7 (Address/ Data Bus) FIGURE 4 – BUS WRITE TIMINti?@PETITOR ADO-AD7 (Address/ Data Bus) Note: VHIGH=VDD-2.O V, VLOW=O.8 V, for VDD=5.O VHIGH=2.O V, VLOW=O.5 V, for VDD=3.O MOTOROLA @ MULTIPLEXED I IL MULTIPLEXED * Address Valid < 10% for outputs only. V for outputs only. ...
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... Description I Oscillator Startu Reset Pulse Width Reset Delay Time DA,.,-. C---- D, ,1-- !AI; A+L DS RESET ITQ All Outputs Except OSC2 (See Figure 10) m MOTOROLA — CHARACTERISTICS (VSS=O Vdc, TA TH) VDD=3.O Vdc I Symbol I Min Max Unit I I lTBDlms]– ltRrl– — ...
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... VDD Pin ~~ Ov RESET Pin CKOUT Pin VDD Pin Ov PS Pin . The VRT bit is set to a ,1’, by reading Register d. The VRT bit mn only be cleared by pulling the PS pin low (see REGISTER D ($OD)). ~ MOTOROLA @ FIGURE 7 – POWER-UP Semiconductor Products Inc. 7 ...
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... CHIP SELECT, INPUT 8.192 kHz The chip-select (C~) signal must be asserted (low) for a bus cycle in which the MC146818A accessed not latched and must be stable during DS and AS (Motorola case of MOTEL) and during ~D and ~R. take place without Register A, as place within the MC146818A ...
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... CO (Maximum 0.012 Cin/Cout 15-30 pF — MOTOROLA @ CONNECTION VDD $ Optional (VDD–1 Oscl 3 (Open)<— OSC2 L MC146818A ,.. ,!~.- OSC2 MC146818A 1.046576 MHz 32.7@ kHz 700 1.7 pF 0.~8 pF 0.~ 15-40 pF 10-22 pF — 300-470 Semiconductor Products Inc. 9 ...
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... IRQ pin is in high-impedance state, j) Square Wave output Enable (SQWE) zero, STBY – STAND– BY The STBY pin, when active, prevents MC146818A making it ideal for battery back-~’~~~l~ations. Stand-by operation incorporates a transpa~~$$~~$tch, data strobe (DS) goes low (TD or _j:rn@), .:>.$,:< J*! recognized as a valid signal ...
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... SCR to appear which may result in excessive and destruction of the part. ADDRESS MAP Figure 14 shows the address map of the MC146818A, memory consists of 50 general purpose RAM bytes, bytes which normally contain the time, calendar, data, and four control ...
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... Writing a “1” interrupt-enable when the event occurs. A “U’ in that interrupt to be initiated the interrupt-enable bit prohibits the IRQ pin from being asserted due to the interrupt cause. MOTOROLA @ AND ALARM DATA Decimal Range Range Binary Data Mode BCD Data Mode ...
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... Again, more than one interrupt-flag DIVIDER STAGES The MC146818A has 22 binary-divider stages following the time base as shown in Figure 1. The output of the dividers signal to the update-cycle controlled by three divider bus (DV2, DVI, Register A ...
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... Periodic Interrupt Time Interval (500 ms, 250 ms, 125 ms, 62,5 ms, etc. per Table 5) tuc = Update Cycle Time ( tBUC = Delay Time Before Update Cycle (2M KS) m MOTOROLA complete, the output will be undefined. gress (UIP) status bit is set during the interval. pin to be triggered ...
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... AF=AIE=”I” UF=UIE=”I” any update cycle in i.e., IRQF= PF*PIE+ AF*AIE+UF*UIE Semiconductor Products Inc. 15 SET is a read/write bit which is not modified of the MC146818A. The periodic interrupt enable (PIE) bit bit which allows the periodic-interrupt flag (PF driven low. A pro- but the periodic flag (P~) bit care” ...
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... Silicon- I Gate CMOS or TTL I Address Decoding I L—— —_ —__ MOTOROLA @ pin is driven low – The remaining They cannot bit on The MC146818A sors which generate Figures 16 and 17 show independent signal processors. The PF bit is decoding can C. metalgate CMOS violated. ...
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... I I This illustrates the use of CMOS gating for address decoding. MOTOROLA @ MULTIPL~ED BUS MICROPROCESSORS m l~Q R ~~8A INTERFACE WITH MC148805W MICROP~@~,SOR WITH SLOW ADDRESSING AS RIW RESET MC146818A VDD MOT CKOUT CKFS STBY ‘ Semiconductor Other + Periph~@ls ...
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... SINGLE CHIP MICROCOMPUTER — M C3870 M C6805 MC 146805 S2000 8021 L——— —— * NOTE: C= can be controlled by a port pin (ifJav}#able). *. ~ADo-AD7 DO-D7 MOTOROLA @ 4. 193W MHz (Tvp) a <$ AS Vss Semiconductor Products Inc. 18 fl_ Power Failure STBY Circuit (See STBY Description) — ...
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... FIGURE 21 – SUBROUTINE THE MCl@18A WITH A NON-MULTIPLIED READ STA RTC LDAB RTC+ 1 RTS STA RTC WRITE STAB RTC+ 1 RTS B MOTOROLA FOR READING AND WRITING BUS Semiconductor Products Inc. 19 ...
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... Inc. Motorola, Inc Equal Employment registered trademarks of Motorola, Semiconductor Products inc. 3501 ED BLUESTEIN BLVD., AUSTIN< TEXAS 78721 . A SUBSIDIARY OF MOTOROLA INC. reliability, function or design. Motorola does neither does it convey any license under its ...