TDA8752B Philips Semiconductors, TDA8752B Datasheet
TDA8752B
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TDA8752B Summary of contents
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... DATA SHEET TDA8752B Triple high-speed Analog-to-Digital Converter 110 Msps (ADC) Preliminary specification Supersedes data of 1999 Nov 11 File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 2000 Jan 10 ...
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... An external clock can also be input to the ADC possible to set the TDA8752B serial bus address between four fixed values, in the event that several TDA8752B ICs are used in a system, using the I interface (for example, two ICs used in an odd/even configuration). PACKAGE ...
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... V = 2.5 V with ref 100 ppm/ C maximum 3 dB 250 amb input signal settling time < amb 100 f = 110 MHz; CLK ramp input f = 66.67 kHz; ref f = 110 MHz CLK 3 Preliminary specification TDA8752B TYP. MAX. UNIT 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 5.0 5.25 V 120 mA 1.0 mA ...
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... OGNDR OGNDB CLAMP MUX OUTPUTS ADC RED CHANNEL GREEN CHANNEL BLUE CHANNEL HSYNCI TDA8752B REGULATOR PLL 2 I C-bus; 1-bit (H level HSYNC DEC1 DEC2 PWDWN CP CZ Fig.1 Block diagram. DGND OGNDPLL 96 82 ...
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... CONTROL AGC ADC ADC MUX V CCAR COARSE GAIN ADJUST HSYNCI RGAINC Fig.2 Red channel diagram. 5 Preliminary specification DAC 8 REGISTER 2 I C-bus; 8 bits (Or) OUTPUTS REGISTER SERIAL 2 I C-bus; 7 bits (Cr C-BUS TDA8752B ROR RBOT FCE468 ...
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... C-bus; 3 bits (Z) VCO 2 I C-bus; phase selector A 2 bits (VCO C-bus; 5 bits (Pa) phase selector C-bus; 5 bits (Pb) Fig.3 PLL diagram. 6 Preliminary specification TDA8752B CKEXT INV MUX 0 /180 2 CLK I C-bus; ADC 1 bit (Cka C-bus; 1 bit (Ckb) NCKBO 1bit ...
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... I C/3W 32 selection input between I 2 ADD1 33 I C-bus address control input 1 2 ADD2 34 I C-bus address control input 2 TCK 35 scan test mode (active HIGH) 2000 Jan 10 DESCRIPTION 2 C-bus (active HIGH) and 3-wire serial bus (active LOW) 7 Preliminary specification TDA8752B ...
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... ADC output bit 7 (MSB green channel ADC output power supply CCOG OGNDR 70 red channel ADC output ground R0 71 red channel ADC output bit 0 (LSB) 2000 Jan 10 DESCRIPTION 2 C-bus/3 W digital power supply 2 C-bus/3 W digital ground 8 Preliminary specification TDA8752B ...
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... PLL coast command input CKREF 94 PLL reference clock input V 95 digital power supply CCD AGNDPLL 96 PLL analog ground CP 97 PLL filter input CZ 98 PLL filter input V 99 PLL analog power supply CCA(PLL) n.c. 100 not connected 2000 Jan 10 DESCRIPTION 9 Preliminary specification TDA8752B ...
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... V CCAG 19 20 GIN AGNDG 21 BAGC 22 BBOT 23 BGAINC 24 BCLP 25 BDEC 26 V CCAB 27 BIN 28 AGNDB 29 n.c. 30 2000 Jan 10 TDA8752BH Fig.4 Pin configuration. 10 Preliminary specification TDA8752B 80 CKREFO V CCOR OGNDR V CCOG ...
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... BOR). It will be at logic 1 when the signal is out of range of the full-scale of the ADCs. Pipeline delay in the ADCs is 1 clock cycle from sampling to data output. The ADCs reference ladders regulators are integrated reference signal is 16 ref ). ref 11 Preliminary specification TDA8752B 1 LSB peak-to-peak variation. 2 ...
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... The reference clock (CKREF) range is between 15 and 280 kHz. Consequently, the VCO minimum frequency is 12 MHz and the maximum frequency 110 MHz for the TDA8752B/8. The gain of the VCO part can be controlled via the serial interface, depending on the frequency range to which the PLL is locked. ...
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... Using two TDA8752Bs the PLL of the master TDA8752B is used to drive both ADC clocks. The PLL of the slave TDA8752B is disconnected and the CKBO of the master TDA8752B is connected to pin CKEXT of the TDA8752B master and CKAO to the slave TDA8752B. In this case, on the CKAO pin CKBO will be the output (with bit CKAB of the master at logic 1) The master TDA8752B is used to sample the even pixels and the slave TDA8752B for odd pixels, using a 180 phase shift between the clocks (CKADCO pins) ...
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... Triple high-speed Analog-to-Digital Converter 110 Msps (ADC) CKREF CKREF Slave at 180 phase shift with respect to pin CKADCO of the master TDA8752B. Fig.6 Dual TDA8752B solution for pixel clock rate with a single phase adjustment (100 to 200 MHz). 2000 Jan 10 COAST CKEXT 12 to ...
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... Fig.7 Clamp definition. N COARSE code 127 G (max) G (min) 99 coarse v alue ref 0.2 0.156 = 16 Fig.8 Coarse gain control. 15 Preliminary specification TDA8752B 2 C-bus and 3-wire serial bus interfaces”. = 120 to 136 clamp programming FCE471 ADC output code 255 227 160 128 V i (p-p) 0.6 2 FCE472 ...
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... Triple high-speed Analog-to-Digital Converter 110 Msps (ADC) coarse register value (67 codes) Fig.9 Fine gain correction for a coarse gain G 2000 Jan 10 ADC output code 255 G (max) 227 N COARSE 160 128 N FINE = 0 N FINE = 31 16 Preliminary specification TDA8752B G NCOARSE G (min) V ref FCE473 . NCOARSE ...
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Acrobat reader. white to force landscape pages to be ... 2 I C-BUS AND 3-WIRE INTERFACES Register definitions The configuration of the different registers ...
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... These bits have to be logic 0 during normal use. The bits Ip0, Ip1 and Ip2 control the charge pump current, to increase the bandwidth of the PLL, as shown in Table 5. = 0). FINE 18 Preliminary specification TDA8752B GAIN FULL-SCALE 0.825 1.212 2 ...
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... Preliminary specification VCO gain V V CO1 CO0 (MHz/ and V control the VCO gain. CO1 CO0 - DOWN MODE PHASEB AND REGISTERS TDA8752B PIXEL CLOCK FREQUENCY RANGE (MHz 110 2 C-bus programming ...
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... The I C-bus address of the circuit is 10011 xx0. Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752Bs can be used on the same system, using the addresses for ADD1 and ADD2 with the not possible to read the data in the register. The timing and protocol for the I are available, see Tables 10 and 11. Table 10 Address sequence for mode 0 ...
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Acrobat reader. white to force landscape pages to be ... 3-wire protocol For the 3-wire serial bus the first byte refers to the register ...
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... Inputs and outputs are protected against electrostatic discharges in normal handling. However totally safe desirable to take normal precautions appropriate to handling integrated circuits. 2000 Jan 10 V CCO DDD V CCD DDD referenced to AGND in free air 22 Preliminary specification CONDITIONS MIN. 0.3 +7.0 0.3 +7.0 0.3 +7.0 0.3 +7.0 1.0 +1.0 1.0 +1.0 1.0 +1.0 1.0 +1.0 0.3 +7 +150 0 70 150 CONDITIONS VALUE 52 TDA8752B MAX. UNIT UNIT K/W ...
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... Fig.8) 23 Preliminary specification CCD (V41) = 4. V59 CCO = CCA DDD CCD CCO MIN. TYP. 4.75 5.0 4.75 5.0 4.75 5.0 4.75 5.0 120 1 0.25 0.25 0.25 0.25 1.1 87 250 4.5 1.67 8 TDA8752B = V95 referenced SSD = 5 V and MAX. UNIT 5.25 V 5.25 V 5. +0.25 V +0.25 V +0.25 V +0. MHz ...
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... Preliminary specification TDA8752B TYP. MAX. UNIT 0 dB 0.5 dB 200 ppm mdB ...
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... COAST(max) t PLL recapture time recap t PLL capture time cap phase shift step step ADCs f maximum sampling frequency TDA8752B/8 s INL DC integral non linearity DNL DC differential non linearity ENOB effective number of bits Signal-to-noise ratio S/N signal-to-noise ratio Spurious free dynamic range ...
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... L referenced to CKADCO 0.4 V 400 2 Preliminary specification TDA8752B TYP. MAX. UNIT 10.1 10 CLK 10.1 + ---------- - 2 0.1 0 1 0.3 0 ...
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... Jan 10 CONDITIONS MIN. 0 4.7 4.0 repeated start 4.7 4.7 4.0 250 0 for f = 100 kHz SCL for f = 100 kHz SCL 4.0 6.02 + 1.76 dB. , which is the time during which the data is d(o) 27 Preliminary specification TDA8752B TYP. MAX. UNIT 100 kHz 1.0 s 300 ns s 400 pF ...
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... Jan 10 t CPH t CPL d(s) sample N 1 sample N Fig.11 Timing diagram. t dHZ HIGH t dZL HIGH 50% 10% 28 Preliminary specification 1 d( h(o) sample N 2 FCE475 50% t dZH 90% 50% LOW S1 3.3 k TDA8752B TDA8752B 2.4 V 1 CCD FCE476 ...
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Acrobat reader. white to force landscape pages to be ... Table 12 Test conditions for Fig.12 TEST SWITCH dLZ CCD t ...
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... V DDD n.c. ADD1 TCK DIS 2 V SSD I C/3W ADD2 TDO SEN SDA V DDD Fig.13 Application diagram. 30 Preliminary specification TDA8752B PWDWN CKBO OE CKADCO CLP V CCO(PLL) OGNDPLL DGND CKAO ...
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... 0.40 0.25 20.1 14.1 24.2 0.65 0.25 0.14 19.9 13.9 23.6 REFERENCES JEDEC EIAJ MO-112 31 Preliminary specification 18.2 1.0 1.95 0.2 0.15 0.1 17.6 0.6 EUROPEAN PROJECTION TDA8752B SOT317 detail X (1) ( 0.8 1 0.4 0.6 0 ISSUE DATE 97-08-01 99-12-27 ...
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... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 32 Preliminary specification TDA8752B ...
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... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Jan 10 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 33 Preliminary specification TDA8752B (1) REFLOW suitable suitable suitable suitable suitable ...
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... I Philips. This specification can be ordered using the code 9398 393 40011. 2000 Jan components conveys a license under the Philips’ system provided the system conforms to the I 34 Preliminary specification TDA8752B 2 C patent to use the 2 C specification defined by ...
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... Philips Semiconductors Triple high-speed Analog-to-Digital Converter 110 Msps (ADC) 2000 Jan 10 NOTES 35 Preliminary specification TDA8752B ...
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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...