PCM1760 Burr-Brown Corporation, PCM1760 Datasheet
PCM1760
Available stocks
Related parts for PCM1760
PCM1760 Summary of contents
Page 1
... The PCM1760/DF1760 pair form a 4-bit, 4th order, 64X oversampling analog-to-digital converter. The PCM1760 is a delta-sigma modulator that uses a 4-bit quantizer within the modulation loop to achieve very high dynamic range. The DF1760 is a high-performance decimating digital filter ...
Page 2
... NOTES: (1) Integrator Constants are determined by the external components shown in the block diagram. (2) FSR means Full Scale Range, digital output code is from 90000H to 70000H, FSR = 5.0V. (3) Use 20-bit DAC, 20kHz LPF, 400Hz HPF, average response. (4) Average response using a 20-bit reconstruction DAC with 20kHz low-pass filter and 400Hz high-pass filter. ® PCM1760P/U DF1760P/U = 48kHz and ext. components = 2% unless otherwise noted. CONDITIONS MIN ...
Page 3
... ABSOLUTE MAXIMUM RATINGS—PCM1760 Supply Voltage ..................................................................................... 6V Voltage Mismatch ............................................................................... 0.1V Analog Input ........................................................................................ V Digital Input ............................................................................... +V Power Dissipation/P ....................................................................... 580mW Power Dissipation/U ....................................................................... 550mW Lead Temperature/P (soldering, 10s) .............................................. 260 C Lead Temperature/U (soldering, 10s) .............................................. 235 C Operating Temperature ......................................................... +70 C Storage Temperature ...................................................... – +125 C ORDERING INFORMATION MODEL PACKAGE ...
Page 4
... CAL SYSCLK BLOCK DIAGRAM OF DF1760 Strobe LRCK V Input SS1 V RAM DD1 Main 256fs Timing Control SYSCLK CLKSEL /PD ® PCM1760P/U DF1760P/U (1) PIN I/O NAME SOIC/DIP 1 O OVL 2 O OVR – TP1 8 – ...
Page 5
... BLOCK DIAGRAM OF PCM1760 RCH In-1R 1R SERVO + AGND Band Gap 7 Bias + – –5V Sub + BGDC In- LCH Out-1R In-2R Out-2R ...
Page 6
... TYPICAL FFT ANALYSIS OF THE 1kHz fs INPUT SIGNAL Frequency (kHz 48.000000kHz F = 1.171876kHz C1 6 OVERALL CHARACTERISTICS OF THE DF1760 (fs) TOTAL PASS-BAND FREQUENCY RESPONSE, COMBINATION OF PCM1760 AND DF1760 1 10 Frequency (kHz 100 ...
Page 7
... BASIC CONNECTION DIAGRAM OF PCM1760 AND DF1760 PCM1760P/U DF1760P/U 7 ® ...
Page 8
... If a 384fs system clock is used, the DF1760 divides by 2/3 to create the 256fs system clock required for the PCM1760. The system clock is applied to pin 15 (SYSCLK input). The actual clock selection is done by setting pin 25 (CLKSEL input) “high” for 256fs clock and “LOW” for 384fs clock ...
Page 9
... NOTE: (1) fs: sampling rate. Fclk: system clock frequency. FIGURE 3f. Power On and Mode Reset Timing. – – – – ns – – ns PCM1760P/U DF1760P SLKH SLKL T T DSS DSV T SLR T SDR T SF NAME MIN TYP ...
Page 10
... DF1760 as close to the unit as possible, preferably to a large ground plane under the PCM1760. The use of a separate +5V supply is recommended for the PCM1760 and DF1760, and to connect the common at one 4Bits Output point as described above. Low impedance analog and digital ADC commons returns are essential for better performance ...
Page 11
... When the sampling frequency (fs) is between 40kHz and 50 kHz and the L/R relative offset voltage ( Vs) is less than or equal to 0.05% of full scale range, the PCM1760 may output a tone similar to an idle tone. This tone is very low and its frequency depends on the input L/R relative offset voltage, Vs. This tone never occurs when the sampling frequency (fs) is 32kHz ...
Page 12
... Input NOTES: (1) Incase of BPZ Error = 0. (2) Overflow detection level is over 70000H or under 82FFFH of digital output code. TABLE I. Output Codes. POWER SUPPLY SEQUENCING The PCM1760 requires V and avoid any possibility of latch-up, the V should all be applied simultaneously or the +V applied first followed by –V and – ...
Page 13
... L/R SCLK NOTE: (1) External /PD input: Time "L" > 2/fs. DF1760P /PD PR OUT D Q CLK Q CL 74HC74 L/R DF1760P /PD PR OUT D Q CLK Q CL 74HC74 L/R PCM1760P/U DF1760P/U 13 SDATA L/R SCLK S /PD LRSC V DD SDATA SDATA L/R L/R SCLK SCLK S /PD LRSC SDATA SDATA L/R L/R SCLK SCLK ® ...
Page 14
... Lch 3 D Lch 2 D Lch 1 D Lch 0 LRCK STROBE FIGURE 14. Input and Output Format of the DF1760 and PCM1760. L/R (I) SCLK (I) FSYNC (I) SDATA (O) M FIGURE 15a. Slave Mode and SCLK = 32fs. (Output format of the DF1760). L/R (I) SCLK (I) FSYNC (I) • MSB First 20-Bit (1) M SDATA (O) • ...
Page 15
... MSB First 16-Bit SDATA (0) LSB First 20-Bit SDATA (0) FIGURE 15c. Slave Mode and SCLK = 64fs. L/R (0) SCLK (0) MSB First 20 Bit (1) FSYNC (0) SDATA (0) MSB First 20 Bit (2) FSYNC (0) SDATA (0) MSB First 16 Bit FSYNC (0) SDATA (0) LSB First 20 Bit FSYNC (0) SDATA (0) FIGURE 15d. Master Mode. PCM1760P/U DF1760P/U 15 ® ...