CS51311GD14 Cherry Semiconductor Corporation, CS51311GD14 Datasheet

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CS51311GD14

Manufacturer Part Number
CS51311GD14
Description
Synchronous CPU Buck Controller for 12V and 5V Applications
Manufacturer
Cherry Semiconductor Corporation
Datasheet
Rev. 3/11/99
100Ω
The CS51311 is a synchronous dual
NFET Buck Regulator Controller. It is
designed to power the core logic of
the latest high performance CPUs. It
uses the V
achieve the fastest possible transient
response and best overall regulation.
It incorporates many additional fea-
tures required to ensure the proper
operation and protection of the CPU
and Power system. The CS51311 pro-
vides the industry’s most highly inte-
grated solution, minimizing external
component count, total solution size,
and cost.
V
Pentium is a registered trademark of Intel Corporation.
2
is a trademark of Switch Power, Inc.
0.01
µ
F
2
TM
VID4
VID2
VID0
VID1
VID3
680pF
0.1
µ
control method to
F
Synchronous CPU Buck Controller
C
COMP
Gnd
OFF
for 12V and 5V Applications
PWRGD
PWRGD
Description
Application Diagram
V
+12V
CC
GATE(H)
GATE(L)
V
V
10K
FB
OUT
1µF
The CS51311 is specifically designed
to power Intel’s Pentium
and includes the following features:
5-bit DAC with 1.2% tolerance,
Power-Good output, over-current
hiccup mode protection, V
soft start, adaptive voltage position-
ing, adaptive FET non-overlap time,
and remote sense. The CS51311 will
operate over an 8.4V to 14V range
and is available in 14 lead narrow
body surface mount package.
FS70VSJ-03
FS70VSJ-03
CS51311
0.1µF
+5V
1.2µH
510Ω
1200µF/10V
510Ω
x3
1
3.3mΩ
®
II processor
CC
monitor,
1200µF/10V
V
2.0V@19A
CC(CORE)
x5
2000 South County Trail, East Greenwich, RI 02818
Tel: (401)885-3600 Fax: (401)885-5786
Cherry Semiconductor Corporation
Synchronous Switching
Dual N-Channel MOSFET
V
200ns Transient Loop
5-bit DAC with 1.2% Tolerance
Hiccup Mode Overcurrent
40ns Gate Rise and Fall Times
65ns Adaptive FET
Adaptive Voltage Positioning
Power-Good Output Monitors
V
Enable Through use of the
Web Site: www.cherry-semi.com
2
CC
V
Regulator Controller for
CPU V
Synchronous Buck Design
Response
Protection
(3.3nF load)
Non-overlap Time
Regulator Output
Voltage Lockout
COMP pin
VID0
VID1
VID2
VID3
VID4
Email: info@cherry-semi.com
TM
V
OUT
Package Options
FB
Monitor Provides Under
Control Topology
14 Lead SO Narrow
Features
1
CORE
A
COMP
C
PWRGD
GATE(L)
Gnd
GATE(H)
V
®
CC
OFF
Company

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CS51311GD14 Summary of contents

Page 1

... COMP pin Package Options 14 Lead SO Narrow VID0 COMP 1 VID1 C OFF VID2 PWRGD VID3 GATE(L) VID4 Gnd V GATE( OUT Cherry Semiconductor Corporation 2000 South County Trail, East Greenwich, RI 02818 Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com A Company ® ...

Page 2

Operating Junction Temperature, T Lead Temperature Soldering Reflow (SMD styles only ...

Page 3

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER Error Amplifier V Bias Current 0.2V ≤V FB COMP Source Current V COMP Sink Current V Open Loop Gain C Unity Gain Bandwidth C ...

Page 4

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER Line Regulation Input Threshold Input Pull-up Resistance Pull-up Voltage GATE(H) and GATE(L) High Voltage at 100mA Low Voltage at 100mA Rise Time Fall Time ...

Page 5

Electrical Characteristics: 0˚C < T 2.0V DAC Code ( ID4 ID3 ID2 PARAMETER General Electrical Specifications V Monitor Start Threshold CC V Monitor Stop Threshold CC Hysteresis V Supply Current CC Note 1: The IC power dissipation ...

Page 6

Figure 1: Gate(H) and Gate(L) Falltime vs. Load Capacitance. 150 V = 12V 125 25°C A 100 2000 4000 6000 8000 10000 Load Capacitance (pF) Figure 2: Gate(H) and Gate(L) Risetime vs. ...

Page 7

The ramp signal also con- tains the DC portion of the output voltage, which allows the control circuit to drive the main ...

Page 8

COMP pin plus the 1.1V PWM comparator offset prior to the drop across the current sense resistor exceeding the current limit threshold. In this case, the PWM control loop has achieved regulation and ...

Page 9

When driving large capacitive loads, the COMP must charge slowly enough to avoid tripping the CS51311 over- current protection. The following equation can be used to ensure unconditional startup − I CHG LIM < COMP OUT ...

Page 10

This causes the regulator to stop switching. During this overcurrent condition, the CS51311 stays off for the time it takes the COMP pin capacitor to discharge to its lower 0.25V threshold. As soon as the COMP ...

Page 11

Number of capacitors = where ESR = maximum ESR per capacitor (specified in CAP manufacturer’s data sheet); ESR = maximum allowable ESR. MAX The actual output voltage deviation due to ESR can then be verified and compared to the value ...

Page 12

EMI. The inductor value can be determined by: (V − × OUT L = ∆Ι where V ...

Page 13

Once the total ESR of the input capacitors is known, the input capacitor ripple voltage can be determined using the formula CIN(RMS) CIN(RMS) where V = input capacitor RMS voltage; CIN(RMS total input RMS current; ...

Page 14

/dt). Unless the gate-drive DG GATE dg dg impedance is very low, the V waveform commonly GS plateaus during rapid changes in the drain-to-source volt- age. The most important aspect of FET performance is the ...

Page 15

Characteristics section switching frequency. SW The total power dissipation in the synchronous (lower) MOSFET can then be calculated as LFET(TOTAL) RMSL where P = Synchronous (lower) FET total losses; LFET(TOTAL Switch Conduction Losses; ...

Page 16

Therefore the error due to sheet resis- tivity is: 1.48 - 1.26 = ±8%. 1.37 2) Mismatch due to L/W The variation in L/W is governed by variations due to the PCB manufacturing process. The ...

Page 17

V TH(TYP CL(NOM) R SENSE(NOM) Maximum Current Limit Setpoint From the overcurrent detection data in the electrical char- acteristics table 101mV, TH(MAX) V TH(MAX CL(MAX SENSE(MIN) SENSE(NOM) 101mV = = ...

Page 18

The input filter inductor may not be required because bulk filter and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. Placement of ...

Page 19

... PACKAGE DIMENSIONS IN mm (INCHES) Lead Count Metric Max 14L SO Narrow 8.75 1.27 (.050) 0.40 (.016) REF: JEDEC MS-012 Ordering Information Part Number Description CS51311GD14 14L SO Narrow CS51311GDR14 14L SO Narrow (tape & reel) Rev. 3/11/99 Package Specification D Thermal Data English R Min Max Min ΘJC 8.55 .344 .337 R Θ ...

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