PCM54 Burr-Brown Corporation, PCM54 Datasheet
PCM54
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PCM54 Summary of contents
Page 1
... Power dissipation with 5V supplies is typically less than 200mW. Also included is a provision for exter- nal adjustment of the MSB error (differential linearity error at bipolar zero, PCM54 only) to further improve Total Harmonic Distortion (THD) specifications if desired. A current output (I output typically settles to within 0 ...
Page 2
... Operating Storage Specifications same as for PCM54HP. NOTES: (1) Externally adjustable. If external adjustment is not used, connect a 0.01 F capacitor to Common to reduce noise pickup. (2) FSR means Full-Scale Range and is 6V for 3V output. (3) The measurement of total harmonic distortion is highly dependent on the characteristics of the measurement circuit. Burr-Brown may calculate THD from the measured linearity errors using Equation 2 in the section on “ ...
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... BPO + MSB Adjust –V CC ABSOLUTE MAXIMUM RATINGS DC Supply Voltage ...................................................................... 18VDC Input Logic Voltage ............................................................... –1V to +5.5V Power Dissipation .................................. PCM54 800mW, PCM55 400mW PACKAGE DRAWING Storage Temperature ...................................................... – +100 C (1) NUMBER Lead Temperature, (soldering, 10s) .............................................. +300 C 215 215 215 ORDERING INFORMATION 178 ...
Page 4
... DLE at bipolar zero (at the “major carry”) can result in (+FSR/2) –1LSB audible crossover distortion for low level output signals. Initial DLE on the PCM54 and PCM55 is factory-trimmed to typically 0.001% of FSR. This error is adjustable to zero using the circuit shown in the connection diagram (PCM54 only) ...
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... The THD is defined as the ratio of the square root of the sum Output of the squares of the values of the harmonics to the value of Mode the fundamental input frequency and is expressed in percent or dB. The rms value of the PCM54/55 error referred to the input can be shown to be: 1.0 10.0 where n is the number of samples in one cycle of any given ...
Page 6
... However, this expression does not mean that the worst-case linearity error of the D/A is directly correlated to the THD. For PCM54/55 the test period was chosen to be 22.7 s (44.1kHz) which is compatible with the EIAJ STC-007 specification for PCM audio. The test frequency is 420Hz and the amplitude of the input signal is 0dB, – ...
Page 7
... Deglitcher Control The deglitcher control signals are generated by the timing control logic. The fast settling time of the PCM54/55 makes it possible to minimize the delay between left and right channels to approximately 4.5 s FIGURE 8. Timing Diagram for the Deglitcher Control Signals. Due to the fast settling time of the PCM54- possible ...