EPM3064xxx Altera, EPM3064xxx Datasheet

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... CO1 f (MHz) 227.3 CNT Altera Corporation DS-MAX3000A-3.4 ® High–performance, low–cost CMOS EEPROM–based programmable logic devices (PLDs) built on a MAX 3.3-V in-system programmability (ISP) through the built–in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – ...

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... Programmable output slew–rate control Software design support and automatic place–and–route provided by Altera’s development systems for Windows–based PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations Additional design entry and simulation support provided by EDIF and netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from third– ...

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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table 2. MAX 3000A Speed Grades Device –4 v EPM3032A v EPM3064A EPM3128A EPM3256A EPM3512A The MAX 3000A architecture supports 100% transistor-to-transistor logic (TTL) emulation and high–density small-scale integration (SSI), medium-scale integration (MSI), and large-scale integration (LSI) logic functions ...

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... MAX 3000A devices can be set for 2 3.3 V, and all input pins are 2.5–V, 3.3–V, and 5.0-V tolerant, allowing MAX 3000A devices to be used in mixed–voltage systems. MAX 3000A devices are supported by Altera development systems, which are integrated packages that offer schematic, text—including VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)— ...

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... Control I/O Block I/O Control I/O Block Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet LAB Macrocells ...

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... Two kinds of expander product terms (“expanders”) are available to supplement macrocell logic resources: The Altera development system automatically optimizes product–term allocation according to the logic requirements of the design. 6 Figure 2 ...

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... operation with programmable clock control. The flipflop can be bypassed for combinatorial operation. During design entry, the designer specifies the desired flipflop type; the Altera development system software then selects the most efficient flipflop operation for each registered function to optimize resource utilization. ...

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... LAB Figure 3 shows how shareable expanders can feed multiple SEXP Shareable expanders can be shared by any or all macrocells in an LAB. 36 Signals 16 Shared from PIA Expanders Macrocell Product-Term Logic Product-Term Select Matrix Macrocell Product-Term Logic Altera Corporation ...

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... Expanders Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The Altera development system compiler can automatically allocate up to three sets five parallel expanders to the macrocells that require additional product terms. Each set of five parallel expanders incurs a small, incremental timing delay (t requires 14 product terms, the compiler uses the five dedicated product terms within the macrocell and allocates two sets of parallel expanders ...

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... MAX 3000A devices. The I/O control block has global output enable signals that are driven by the true or complement of two output enable signals, a subset of the I/O pins subset of the I/O macrocells. 10 Figure 5 PIA Signals shows how the PIA signals are routed . Figure 6 shows the I/O CC Altera Corporation To LAB ...

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... Figure 6. I/O Control Block of MAX 3000A Devices PIA Note: (1) EPM3032A, EPM3064A, EPM3128A, and EPM3256A devices have six output enables. EPM3512A devices have 10 output enables. Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet to Other I/O Pins from Macrocell to PIA When the tri–state buffer control is connected to ground, the output is tri-stated (high impedance), and the I/O pin can be used as a dedicated input. When the tri– ...

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... The IEEE Std. 1532 is a standard developed to allow concurrent ISP between multiple PLD vendors. 12 Application Note 88 (Using the Jam Language for ISP & ICR via Processor), Application Note 122 (Using Jam STAPL for ISP & and AN 111 (Embedded Programming Using Byte-Code). Altera Corporation ...

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... EEPROM cells. This process is repeated for each EEPROM address. 5. Verify. Verifying an Altera device in-system involves shifting in addresses, applying the read pulse to verify the EEPROM cells, and shifting out the data for comparison. This process is repeated for each EEPROM address. ...

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... EEPROM cells Cycle = Number of TCK cycles to program a device PTCK f = TCK frequency TCK C ycle VTC -------------------------------- VER VPULSE Verify time VER t = Sum of the fixed times to verify the EEPROM cells VPULSE Cycle = Number of TCK cycles to verify a device VTCK Altera Corporation ...

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... Table 6. MAX 3000A Stand-Alone Verification Times for Different Test Clock Frequencies Device 10 MHz 5 MHz EPM3032A 0.00 EPM3064A 0.01 EPM3128A 0.01 EPM3256A 0.02 EPM3512A 0.03 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet The programming times described in with the worst-case method using the enhanced ISP algorithm. & Cycle Values TCK Programming t (s) Cycle PPULSE 2.00 55,000 2 ...

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... MAX 3000A devices include the JTAG BST circuitry defined by IEEE Std. 1149.1–1990. 1149.1 (JTAG) MAX 3000A devices. The pin-out tables found on the Altera web site (http://www.altera.com) or the Altera Digital Library show the location of Boundary–Scan the JTAG control pins for each device. If the JTAG interface is not Support required, the JTAG pins are available as user I/O pins ...

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... Notes: (1) The most significant bit (MSB the left. (2) The least significant bit (LSB) for all JTAG IDCODEs is 1. See Application Note 39 (IEEE 1149.1 (JTAG) Boundary–Scan Testing in Altera Devices) for more information on JTAG BST. Tables 8 and Boundary–Scan Register Length ...

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... Update register high impedance to valid output JSZX t Update register valid output to high impedance JSXZ t t JPSU JPH t JPCO t JSH t t JSCO JSXZ Min 100 Altera Corporation t JPXZ Max Unit ...

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... Speed/Power Control Output Configuration Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A devices offer a power–saving mode that supports low-power operation across user–defined signal paths or the entire device. This feature allows total power dissipation to be reduced by 50% or more because most logic applications require only a small fraction of all gates to operate at maximum frequency ...

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... AC test measurements are taken under conditions equivalent to those shown in erased during early stages of the production flow. 20 When MAX 3000A device can drive a 2.5–V device that has 3.3–V CCIO tolerant inputs. Figure current specification should Test patterns can be used and then Altera Corporation . IH ...

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... STG T Ambient temperature A T Junction temperature J Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Figure 8. MAX 3000A AC Test Conditions Power supply transients can affect AC measurements. Simultaneous transitions of multiple outputs should be avoided for accurate measurement. Threshold tests must not be performed under AC conditions. Large– ...

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... Min Max 3.0 3.6 3.0 3.6 2.3 2.7 3.0 3.6 –0.5 5. CCIO 0 70 – –40 105 40 40 Min Max 1.7 5.75 –0.5 0.8 2.4 (5) V – 0.2 CCIO (5) 2.1 2.0 1.7 0.4 0.2 0.2 0.4 0.7 –10 10 – Altera Corporation Unit ° C ° C ° C ° Unit ...

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... I/O pin capacitance I/O Notes to tables: (1) See the Operating Requirements for Altera Devices Data (2) Minimum DC input voltage is –0.5 V. During transitions, the inputs may undershoot to –2 overshoot to 5.75 V for input currents less than 100 mA and periods shorter than 20 ns. (3) All pins, including dedicated inputs, I/O pins, and JTAG pins, may be driven before V powered ...

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... O 2.5 V 150 100 Typical I O Output Current (mA Output Voltage (V) O and V CCIO 3.3 V CCINT V = 3.3 V CCI Temperature 3.3 V CCINT V = 2.5 V CCI Temperature power planes can be CCINT Altera Corporation ...

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... PIA Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet MAX 3000A device timing can be analyzed with the Altera software, with a variety of popular industry–standard EDA simulators and timing analyzers, or with the timing model shown in devices have predictable internal delays that enable the designer to determine the worst– ...

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... Logic Array Clock at Register Data from Logic Array Register to PIA to Logic Array Register Output to Pin t PIA t SEXP LAC LAD t PEXP t COMB ACL PIA t OD Altera Corporation PIA CLR PRE t OD ...

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... Maximum internal CNT global clock frequency t Minimum array clock ACNT period f Maximum internal ACNT array clock frequency Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Tables 16 through 23 show EPM3032A, EPM3064A, EPM3128A, EPM3256A, and EPM3512A timing information. Note (1) Conditions –4 Min ...

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... CLR t PIA delay PIA 28 Conditions –4 Min Max 0.7 0.7 1.9 0.5 1.5 0 9.0 4.0 1.3 0.6 0.7 0.6 1.2 0.6 0.8 1.2 1.2 (2) 0.9 Note (1) Speed Grade –7 –10 Min Max Min Max 1.2 1.5 1.2 1.5 3.1 4.0 0.8 1.0 2.5 3.3 1.0 1.2 0.0 0.0 1.3 1.8 1.8 2.3 6.3 6.8 4.0 5.0 4.5 5.5 9.0 10.0 4.0 5.0 2.0 2.8 1.0 1.3 1.2 1.5 1.0 1.3 2.0 2.5 1.0 1.2 1.3 1.9 1.9 2.6 1.9 2.6 1.5 2.1 Altera Corporation Unit ...

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... Minimum global clock CNT period f Maximum internal global CNT clock frequency t Minimum array clock period ACNT f Maximum internal array ACNT clock frequency Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions –4 Min Max (5) 2.5 Note (1) Conditions –4 Min Max (2) 4 ...

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... PRE t Register clear time CLR 30 Conditions –4 Min Max 0.6 0.6 1.8 0.4 1.5 0 9.0 4.0 1.3 0.6 0.7 0.6 1.2 0.6 1.0 1.3 1.3 Note (1) Speed Grade –7 –10 Min Max Min Max 1.1 1.4 1.1 1.4 3.0 3.9 0.7 0.9 2.5 3.2 1.0 1.2 0.0 0.0 1.3 1.8 1.8 2.3 6.3 6.8 4.0 5.0 4.5 5.5 9.0 10.0 4.0 5.0 2.0 2.9 1.0 1.3 1.2 1.6 0.9 1.3 1.9 2.5 1.0 1.2 1.5 2.2 2.1 2.9 2.1 2.9 Altera Corporation Unit ...

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... CPPW for clear and preset t Minimum global clock CNT period f Maximum internal CNT global clock frequency t Minimum array clock ACNT period Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions –4 Min (2) (5) Note (1) Conditions –5 Min Max 5.0 ...

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... Min Speed Grade –7 –10 Min Max Min 129.9 98.0 Note (1) Speed Grade –7 –10 Max Min Max Min 0.7 1.0 0.7 1.0 2.0 2.9 0.4 0.7 1.6 2.4 0.7 1.0 0.0 0.0 0.8 1.2 1.3 1.7 5.8 6.2 4.0 4.0 4.5 4.5 9.0 9.0 4.0 4.0 Altera Corporation Unit Max MHz Unit Max 1.4 ns 1.4 ns 3.8 ns 0.9 ns 3.1 ns 1.3 ns 0.0 ns 1.6 ns 2.1 ns 6.6 ns 5.0 ns 5.5 ns 10.0 ns 5.0 ns ...

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... Array clock hold time AH t Array clock to output delay ACO1 t Array clock high time ACH t Array clock low time ACL t Minimum pulse width for CPPW clear and preset Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions –5 Min Max 1.4 0.6 0.8 0.5 1.2 0.7 1.1 1.4 1.4 (2) 1 ...

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... Conditions 3 2.5 V Speed Grade –7 –10 Max Min Max 7.9 10.5 95.2 7.9 10.5 95.2 Note (1) Speed Grade –7 –10 Min Max Min Max 0.9 1.2 0.9 1.2 2.8 3.7 0.5 0.6 2.2 2.8 1.0 1.3 0.0 0.0 1.2 1.6 1.7 2.1 6.2 6.6 4.0 5.0 4.5 5.5 Altera Corporation Unit ns MHz ns MHz Unit ...

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... Global clock to output delay CO1 t Global clock high time CH t Global clock low time CL t Array clock setup time ASU t Array clock hold time AH Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Note (1) Conditions –7 Min 2.1 0.9 (2) (5) Note (1) Conditions ...

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... CCIO 36 Note (1) Conditions Speed Grade -7 Min Max (2) 1.0 7.8 3.0 3.0 (3) 3.0 (2) 8.6 (2), (4) 116.3 (2) 8.6 (2), (4) 116.3 Note (1) Conditions Speed Grade -7 Min Max 0.7 0.7 3.1 2.7 0.4 2.2 1 6.0 Unit -10 Min Max 1.0 10.4 ns 4.0 ns 4.0 ns 4.0 ns 11.5 ns 87.0 MHz 11.5 ns 87.0 MHz Unit -10 Min Max 0.9 ns 0.9 ns 3.6 ns 3.5 ns 0.5 ns 2.8 ns 1.3 ns 0.0 ns 1.5 ns 2.0 ns 6.5 ns Altera Corporation ...

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... These parameters are measured with a 16–bit loadable, enabled, up/down counter programmed into each LAB. (5) The t parameter must be added to the t LPA running in low–power mode. Power Consumption Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Conditions (2) ...

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... MAX 3000A Programmable Logic Device Family Data Sheet The P and switching frequency, can be calculated using the guidelines given in Application Note 74 (Evaluating Power for Altera The I logic. The The parameters in the tog The I conditions using a pattern of a 16–bit, loadable, enabled, up/down counter in each LAB with no output load ...

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... Typical I CC Active (mA Low Power 100 Frequency (MHz) Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet EPM3064A 227.3 MHz High Speed Typical I Active (mA) 144.9 MHz Low Power 200 250 192.3 MHz High Speed 108 ...

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... Low Power Frequency (MHz) 40 EPM3512A 172.4 MHz High Speed Typical I Active (mA) 102.0 MHz 100 200 600 Room Temperature 500 400 High Speed CC 300 76.3 MHz 200 Low Power 100 Frequency (MHz) Altera Corporation 116.3 MHz 100 120 140 ...

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... PLCC Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet See the Altera web site (http://www.altera.com) or the Altera Digital Library for pin–out information. Figures 14 through 18 show the package pin–out diagrams for MAX 3000A devices ...

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... Figure 15. 100–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale. Figure 16. 144–Pin TQFP Package Pin–Out Diagram Package outline not drawn to scale 42 Pin 1 EPM3064A EPM3128A Pin 26 . Indicates location of Pin 1 Pin 1 EPM3128A EPM3256A Pin 37 Pin 76 Pin 51 Pin 109 Pin 73 Altera Corporation ...

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... Figure 17. 208–Pin PQFP Package Pin–Out Diagram Package outline not drawn to scale Pin 1 Pin 53 Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet . EPM3256A EPM3512A Pin 157 Pin 105 43 ...

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... Updated Table 1. Updated Tables 3, 13, and 26. Added Tables 4 through 6. Updated Figures 12 and 13. Added “Programming Sequence” on page 13 Times” on page and “Programming Altera Corporation A1 Ball Pad Corner ...

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... Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Version 3.2 The following change were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.2: Updated the EPM3512 I Version 3.1 The following changes were made in the MAX 3000A Programmable Logic Device Data Sheet version 3.1: ...

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... Copyright © 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the (408) 544-7000 stylized Altera logo, specific device designations, and all other words and logos that are identified as http://www.altera.com trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Applications Hotline: Corporation in the U ...