SAA7385GP Philips Semiconductors, SAA7385GP Datasheet

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SAA7385GP

Manufacturer Part Number
SAA7385GP
Description
Error correction and host interface IC for CD-ROM SEQUOIA
Manufacturer
Philips Semiconductors
Datasheet

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SAA7385GP
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Preliminary specification
File under Integrated Circuits, IC01
DATA SHEET
SAA7385
Error correction and host interface
IC for CD-ROM (SEQUOIA)
INTEGRATED CIRCUITS
1996 Jun 19

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SAA7385GP Summary of contents

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DATA SHEET SAA7385 Error correction and host interface IC for CD-ROM (SEQUOIA) Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 1996 Jun 19 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) CONTENTS 1 FEATURES 1.1 General 1.2 53CF94 SCSI controller 1.3 80C32 high-speed microcontroller 1.4 Front-end interface logic 1.5 Buffer controller 1.6 Hardware third-level error correction 1.7 Additional product support 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 1 FEATURES 1.1 General Single chip digital solution for an 8 controller chip 10 Mbytes/s NCR53CF94 equivalent SCSI controller included High-speed 80C32 microcontroller with 256 scratch-pad SRAM included High performance CD-ROM interface logic 128 pin QFP package. ...

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... ORDERING INFORMATION TYPE NUMBER NAME SAA7385GP SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm); body 14 1996 Jun 19 Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 5 BLOCK DIAGRAM handbook, full pagewidth data subcode CD DECODER C-flag S2B serial interface SERVO PROCESSOR 6 PINNING All input, output and bidirectional signals are TTL level unless otherwise stated (Pull-Down = PD25 = 25 A; Pull-Up = PU25 = 25 A, PU400 = 400 A; Slew = mA mA; ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL PIN I/O RAS 11 O CAS 12 O DWR 13 O DOE SS2 DD0 16 I/O DD1 17 I/O DD2 18 I/O DD3 19 I DD2 DD4 21 I/O DD5 22 I/O DD6 23 I/O DD7 24 I SS3 LED 26 O TRAYSW 27 I EJECT 28 I LQDATA ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL PIN I/O LA1 52 O LA2 53 O LA3 DD4 LA4 56 O LA5 57 O LA6 58 O LA7 SS7 A10 63 O A11 64 O A12 65 O A13 66 O A14 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL PIN I/O RXS2B 93 I TXS2B 94 O TRAYIN 95 I/O TRAYOUT 96 I/O SCSIRST 97 I POR DD6 UC_PORT1.7 100 I/O RAB_MUSB 101 I/O NRST_SEQ 102 I/O UC_PORT1.4 103 I/O UC_PORT1.3 104 I/O UC_PORT1.1 105 I/O HOMESW 106 I/O PLAY 107 I UC_PORT1.6 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth UC_PORT1.4 103 UC_PORT1.3 104 UC_PORT1.1 105 106 HOMESW 107 PLAY UC_PORT1.6 108 V SS13 109 GPI1 110 GPI2 111 112 KILL TXICE 113 RXICE 114 RXSUB 115 V DD7 116 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 1996 Jun 19 10 Preliminary specification SAA7385 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 7 FUNCTIONAL DESCRIPTION 7.1 80C32 microcontroller The standard specification for details of the operation for this part may be found in any data sheet covering the 80C32 microcontroller. The one deviation from a normal 80C32 is the addition of all of the control registers for the special function register map for the 80C32 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 7.4.4 C-F R LAG ECEIVER The C-flag bits, or corrector flags, are also 24 data clocks long and reception of these bits is achieved using the same method as for the sub-code; in this event, the C-flag data is synchronized to the data. The difference is that only one bit is used ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA DOE handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA WRITE 1996 Jun 19 ROW COL latch low nibble Fig.4 Nibble access read cycle. ROW ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA DOE handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA WRITE 1996 Jun 19 ROW COL Fig.6 Byte mode single access read cycle. ROW COL DATA Fig ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA DOE handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA WRITE 1996 Jun 19 COL1 COL2 latch Fig.8 ECC burst access read cycle. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA DOE handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA WRITE 1996 Jun 19 COL1 COL2 latch data Fig.10 SCSI standard burst access read cycle. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 8 MICROCONTROLLER INTERFACE 8.1 Microcontroller interface status register Table 1 NUM_COR register: 0xF08E MNEMONIC R/W 7 NUM_COR R Register 0xF08E indicates the number of corrections performed during the most recently executed CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command. Note that NUM_COR is only valid after completion of the CORRECT_P_SYNDROMES or CORRECT_Q_SYNDROMES command, and becomes invalid upon execution of any other command ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 5 Definitions of ECC_COMMAND3 to ECC_COMMAND0 EEC_COMMAND 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1100 1101 1110 Table 6 Command descriptions COMMAND ASSERT_ABORT RELEASE_ABORT CRC_RECALCULATE CALCULATE_SYNDROMES 1996 Jun 19 ASSERT_ABORT RELEASE_ABORT ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) COMMAND COPY_RESULTS CORRECT_P_SYNDROMES CORRECT_Q_SYNDROMES TEST_ECC_ROM TEST_ECC_RAM_READ TEST_ECC_RAM_WRITE Note 2075 and 0 : 2067 are address frame offsets. The frame buffer organization is shown in Table 75. 8.3 Microcontroller interrupts An interrupt pulse is generated upon completion of any of the following commands: ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 7 Command execution times COMMAND CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES (maximum addition per correction) ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 10 INTRFLG field descriptions FIELD FRM_STR STR_LST FE_2352 FE_HDR ECC_COR RFERXINT FETXINT 8.4 Microcontroller RAM organization MICFRM# is used to determine the frame address for the microcontroller access through the frame window 0x8000 to 0x8FFF. To obtain the actual byte location within the buffer RAM, the lower 12 bits of the microcontroller address form the relative offset and hence the absolute address is found ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 12 Microcontroller address page register: 0xF0FF MNEMONIC R/W 7 PAGEREG R/W Note 1. PAGE_EN is disconnected. Register 0xF0FF is used by the buffer manager for the upper address lines when the microcontroller addresses non-frame memory. These registers overlap frame memory, so register 0xF0FF must be programmed with an address in the top part of the memory if no overlap is required ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, halfpage Table 15 SAA7385 address map details for the 80C32 ADDRESS 0000 to 7FFF This 32 kbyte window is used to address and portion the DRAM buffer intended for non-frame mapped memory to be addressed through this window. The upper page address bits (to address the full range of the DRAM buffer) are set by the linear address page register (PAGEREG) ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 9 FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS This chapter describes the various SAA7385 control signals; front panel and basic engine signals, jumper settings and use of the general purpose signals. Table 16 Start clock doubler: 0xF091 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 20 General logic control register: 0xF0B9; note 1 MNEMONIC R/W 7 WTGCTL W Note 1. Register 0xF0B9 controls the audio mixing and the LED. Table 21 WTGCTL field description FIELD LOGIC CHANNELS 00 mute 01 right data sent to both channels ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 25 RDJMPRS field description FIELD JUMPER7 to JUMPER0 Indicates the value of the DRAM data bus on power-up. The data bus may be pulled HIGH or LOW using weak pull-ups and pull-downs hence up to eight jumper settings are accommodated. Table 26 General purpose bits: 0xF0C2 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 9.1 S2B UART registers This section describes the registers used for the S2B UART control. Table 28 S2B UART transmit, receive and status buffer: 0xF0A1, F0A2 and F0A3 MNEMONIC R/W 7 (1) WTS2B W DATA7 RDS2B ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 31 BRGSEL field description FIELD LOGIC ICESEL1 31.25 kbaud transfer rate 01 62.5 kbaud transfer rate 10 187.5 kbaud transfer rate 11 not specified INVQ inverts all Q-channel information if set INVSUBC inverts all sub-code information if set ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 9.2 Miscellaneous control registers Table 34 53CF90 direction and audio mode control: 0xF0C1; note 1 MNEMONIC R/W 7 AUSWP R/W TEST Note 1. Register 0xF0C1 controls the audio mode byte swapping and a test mode bit. Table 35 WTDIR field descriptions ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 38 DRAM selection/test mode: 0xF0FE; note 1 MNEMONIC R/W 7 DRAMSEL R/W TEST Note 1. After power-up or reset, DRAMSEL should be the first register that is programmed. This register is used to select the number and the type of DRAMs used. The output of this register is used to control the DRAM access directly and will affect any current DRAM cycle. Table 39 SCSIMOD fi ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 10 FRONT-END This Chapter explains the information of the front-end circuitry. 10.1 Minute Second Frame (MSF) addressing and header information Table 40 Header mode and MSF from block decoder: 0xF092, F093, F09A and F09B MNEMONIC ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 10.2 Front-end status and control Table 43 Front-end control: 0xF0BB; note 1 MNEMONIC R/W 7 FECTL R/W SIM_EOF Note 1. Register 0xF0BB controls the front-end of the SAA7385. The naming convention used here is similar to that used in the block decoders. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 45 Read status register: 0xF0C3; note 1 MNEMONIC R/W 7 RDDSTAT R DCOTACT Note 1. The information in register 0xF0C3 is a copy of the status byte written to the data buffer at the end of every frame. SYNCERR, DATERR and CRCERR are essentially unusable since they are valid only long enough to be written to the buffer. Table 46 RDDSTAT fi ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 11 BUFFER MANAGER 11.1 Front-end to buffer manager interface The buffer manager interface to the front-end is write only with no handshaking. The front-end passes one byte of data and a write strobe to the buffer manager; this byte will be one of five types of data (see Table 47). The data byte is latched and the interface is given the highest priority thus no wait signal is required ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 49 Front-end frame number: 0xF0E4, F0E5 MNEMONIC R/W 7 FEFRM# R/W NUM7 FEFRM# R/W This register allows the front-end frame number counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 51 Last complete frame number: 0xF0E6, F0E7 MNEMONIC R/W 7 LSTCMPFM R NUM7 LSTCMPFM R 11.3 ECC to buffer manager interface The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides an offset address and uses a frame address programmed by the microcontroller, ECCFRM# ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) transferred, the second offset block as specified by SCSIOFFS-B and SCSIOFFE-B is transferred. The frame address will not be incremented until after both offset blocks are transferred. Once both offset blocks are transferred, the frame address is incremented and again the two offset blocks are transferred for the next frame ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 54 SCSI offset end registers (A and B): 0xF0EA, F0EB; note 1 MNEMONIC R/W 7 SCSIOFFE R/W SCSIOFFE R/W Note 1. These registers together with the offset start registers, allow full control over the number of frame bytes that will be transferred to the SCSI port. Table 55 SCSI transfer start frame number: 0xF0EC, F0ED ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 11.6 53CF94 related registers In the 53CF94 SCSI controller, some registers are read only and others are write only. These share the same address and the multiplexing between the two depends on the read or write select. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 61 STAT field description FIELD MSG, C/D, I/O These indicate the phase on the SCSI bus. VGC Valid Group Code; set if the group code matches code defined in ANSI X3.131-1986. TC Terminate Count; set when transfer count decrements to zero. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 65 SEQSTP field descriptions FIELD SS2 to SS0 Sequence step. Counter increments at various points in a command; may be used for error recovery. SOM Synchronous offset maximum. When clear, the synchronous offset has reached the maximum value. TRANSPERIOD Synchronous transfer period. Specifi ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 69 CONFIG1 to CONFIG4 field descriptions FIELD MyBusID ID of SCSI controller CTEST chip test mode enable PCHK enable parity checking PTEST parity test mode SRD SCSI reset reporting interrupt disable SLOW slow cable mode ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) Table 72 Test Register: 0xF06 - 53CF94 address 0x0A; note 1 MNEMONIC R/W 7 TEST R/W Note 1. This register is enabled by setting the test mode in CONFIG1; after test mode is entered, a hardware reset or reset command must occur before normal operation may resume. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 12 FRAME BUFFER ORGANIZATION Table 75 Frame buffer organization DECIMAL START END 2063 2064 2067 2068 2075 2076 2247 2248 2351 2352 2367 2368 2463 2464 2757 2758 2761 2762 2933 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 13 SUMMARY OF CONTROL REGISTER MAP Table 77 Control register map for the SAA7385 ADDRESS MNEMONIC F085 ECCCTL F086 ECCSTAT F08E NUM_COR F091 CLKSEL F092 MODE F093 FRMS F09A SECS F09B MINS F09E UARTCTL ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) ADDRESS MNEMONIC F0C1 AUSWP F0C2 GPIOCTL F0C3 RDDSTAT F0C9 RDJMPRS F0D8 FSTEST F0E2 FEFRMOFF F0E3 FEFRMOFF F0E4 FEFRM# F0E5 FEFRM# F0E6 LSTCMPFM F0E7 LSTCMPFM F0E8 SCSIOFFS F0E9 SCSIOFFS F0EA SCSIOFFE F0EB ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL V digital supply voltage DD V maximum input voltage on any pin i(max) V output voltage on any output o T storage temperature stg 15 OPERATING CHARACTERISTICS 2 15 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.2 EIAJ timing; audio mode V = 4. SYMBOL PARAMETER EIAJ timing (single speed n); see Fig.14 and note CLAB LOCK INPUT T output clock period cy t clock HIGH time CH t clock LOW time ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth CLAB DAAB 1 WSAB EFAB left LSB valid (error flags) CLAB DAAB WSAB EFAB CLAB handbook, full pagewidth DAAB 1 0 WSAB EFAB CLAB DAAB WSAB EFAB 1996 Jun ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.3 R-W timing (see Fig.15) The data from sub-code R-W may be read via the V4 pin from the CD-decoder and has a format similar to RS232. The sub-code synchronization word is formatted by a pause of 200 s minimum. Each sub-code byte starts with a logic 1 followed by seven bits ( ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.5 S2B interface timing The S2B serial interface consists of four lines (see Fig.17): Transmit data (TXD) Receive data (RXD) Data path ready to accept data; active LOW (CPR) Basic engine ready to accept data; active LOW (SPR). ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.6 SCSI interface timing V = 4. SYMBOL PARAMETER Target asynchronous send; see Fig.19 t Data set-up time to REQ LOW 1 t ACK LOW to REQ HIGH 2 t Data hold time from ACK LOW ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth REQ ACK SD7 to SD0 handbook, full pagewidth SD7 to SD0 REQ/ACK handbook, full pagewidth SD7 to SD0 REQ/ACK 1996 Jun Fig.20 Target asynchronous receive signal transitions Fig ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.7 Microprocessor interface V = 4. SYMBOL Program memory fetch timing; see Fig.23 t address valid to ALE LOW AVLL t address hold after ALE LOW LLAX t ALE LOW to PSEN LOW LLPL t PSEN pulse width ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 15.8 DRAM interface (the SAA7385 is designed to operate with standard 70 ns DRAMs 4. SYMBOL DRAM interface timing; see Figs access time from column address acc;CA t column address hold time from RAS hCA ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) SYMBOL t write command to RAS lead time RASL;W t transition time (rise or fall) trans t write command hold time hW t write command hold time (referenced to RAS) hW;RAS t WE command set-up time su;WE t write command pulse width W ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth RAS t pCAS;RAS CAS t su;RA ADDRESS DATA 1996 Jun 19 t cy;R/W t W;RAS t h;CAS t dRAS;CAS t hCA;RAS t dRAS;CA t h;RA t su;CA t h;CA COLUMN ROW t hDAT;RAS t su;DAT Fig.25 DRAM early write cycle. 57 Preliminary specification t pRAS t h;RAS t W ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 1996 Jun 19 58 Preliminary specification SAA7385 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 1996 Jun 19 59 Preliminary specification SAA7385 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) handbook, full pagewidth ADDRESS 1996 Jun 19 t cy;R/W t W;RAS RAS t pCAS;RAS CAS t su;RA t h;RA ROW Fig.28 DRAM refresh cycle. 60 Preliminary specification t pRAS t pRAS;CAS ROW MGE416 SAA7385 ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 16 PACKAGE OUTLINE SQFP128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 2 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions UNIT max. ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 17 SOLDERING 17.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...

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... Philips Semiconductors Error correction and host interface IC for CD-ROM (SEQUOIA) 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. ...

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... Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. + 24825 © Philips Electronics N.V. 1996 All rights are reserved ...

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