SAA7390GP Philips Semiconductors, SAA7390GP Datasheet

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SAA7390GP

Manufacturer Part Number
SAA7390GP
Description
High performance Compact Disc-Recordable CD-R controller
Manufacturer
Philips Semiconductors
Datasheet
Preliminary specification
File under Integrated Circuits, IC01
DATA SHEET
SAA7390
High performance Compact
Disc-Recordable (CD-R) controller
INTEGRATED CIRCUITS
1996 Jul 02

Related parts for SAA7390GP

SAA7390GP Summary of contents

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DATA SHEET SAA7390 High performance Compact Disc-Recordable (CD-R) controller Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 1996 Jul 02 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller CONTENTS 1 FEATURES 1.1 General 1.2 Interface logic (CD-ROM operation) 1.3 Hardware third-level error correction 1.4 Interface logic (CD-R operation) 1.5 DRAM buffer controller (256 kbytes 1 Mbyte 8, 4 Mbytes 1.6 Additional product support 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 1 FEATURES 1.1 General 8 speed CD-ROM, 4 speed Compact Disc-Recordable (CD-R) controller 16.9 Mbytes/s burst rate to host controller High performance CD-ROM and CD-R interface logic 128 pin QFP package. 1.2 Interface logic (CD-ROM operation) Full 8 speed hardware operation Block decoder Sector sequencer ...

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... DD T operating ambient temperature amb T storage temperature stg 4 ORDERING INFORMATION TYPE NUMBER NAME (1) SAA7390GP SQFP128 plastic quad flat package; 128 leads (lead length 1.6 mm); body 14 Note 1. This device uses a Symbios logic package. 1996 Jul 02 PARAMETER PACKAGE DESCRIPTION 20 2 Preliminary specification SAA7390 MIN ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 5 BLOCK DIAGRAM handbook, full pagewidth data DATA CONVERTER AND SUB-CODE UART data subcode CD DECODER C-flag BASIC WRITE I/F ENGINE MGE518 6 PINNING All input and bidirectional signals are TTL level with Schmitt-trigger logic, with the exception of OSCIN. All output signals are TTL levels unless otherwise stated. (PD = internal pull-down ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller SYMBOL PIN I/O DA7 DD1 DA8 12 O DA9 13 O DA10 14 O RAS 15 O CAS 16 O DWR 17 O DOE 18 O DD0 19 I DD2 DD1 21 I/O DD2 22 I/O DD3 23 I/O DD4 24 I SS3 DD5 26 I/O DD6 27 I/O DD7 28 I/O COM_IN 29 I COM_OUT ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller SYMBOL PIN I/O UC_AD2 51 I/O UC_AD3 52 I SS6 UC_AD4 54 I/O UC_AD5 55 I/O UC_AD6 56 I/O UC_AD7 57 I DD5 UC_LA0 59 O UC_LA1 60 O UC_LA2 SS7 UC_LA3 63 O UC_LA4 64 O UC_LA5 65 O UC_LA6 66 O UC_LA7 SS8 PCLK ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller SYMBOL PIN I/O SD5 92 I/O SD6 93 I/O SD7 94 I SS10 DREQ 96 I DACK 97 O HOSTRD 98 O HOSTWR 99 O HOSTSEL 100 O CSAB 101 I CCLAB 102 I CDAAB 103 O RXS2B 104 I TXS2B 105 O CPR 106 O SCSIRST 107 I POR 108 I TCL_GPIO1 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CDAAB 103 RXS2B 104 105 TXS2B 106 CPR 107 SCSIRST 108 POR TCL_GPIO1 109 110 SPR TDA_GPIO2 111 112 HFD 113 KILL V SS11 114 115 MCOUT 116 MCIN RXSUB 117 CFLAG ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller dbook, full pagewidth 1996 Jul 02 10 Preliminary specification SAA7390 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 7 FUNCTIONAL DESCRIPTION 7.1 Input clock doubler To facilitate compatibility of the SAA7390 with all of the available CD decoders, a clock doubler has been included. This clock doubler may take a 16.9344 MHz clock and double this when requested the microcontroller. Logic has been included to remove the possibility of a ‘ ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller When the ten Q-channel registers have been updated, QFRMRDY in RDDSTAT is set. The ten Q-channel registers are valid while QFRMRDY is set. In the audio mode, HDRRDY in RDDSTAT generates this interrupt, but the QFRMRDY bit will still be available as status to the microcontroller ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 7.5 Buffer manager The buffer manager provides the arbitration for the different processes that wish to access the DRAM buffer. These processes include the front-end, microcontroller requests, CDB2 accesses, ECC accesses, host interface requests and DRAM refreshing. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CLOCK RAS CAS ADDRESS DATA WRITE handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA DOE 1996 Jul 02 ROW COL DATA Fig.5 Byte mode single access write cycle. COL1 COL2 latch Fig ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA WRITE handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA DOE Fig.8 Host interface fast burst access read cycle (2 clocks). 1996 Jul 02 COL1 COL2 DATA1 DATA2 Fig ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA WRITE Fig.9 Host interface fast burst access write cycle (2 clocks). handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA DOE Fig.10 Host interface standard burst access read cycle (3 clocks). ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CLOCK RAS CAS ADDRESS ROW DATA WRITE Fig.11 Host interface standard burst access write cycle (3 clocks). 8 MICROCONTROLLER INTERFACE 8.1 Microprocessor interface status register Table 1 NUM_COR register: 0xF08E; note 1 MNEMONIC R/W NUM_COR R Note 1 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 3 ECCSTAT definitions MNEMONIC ECC_ACT asserted while a command other than ASSERT_ABORT or RELEASE_ABORT remains active QS_EQ0 asserted when all Q syndromes are zero PS_EQ0 asserted when all P syndromes are zero CRC_EQ0 asserted when the CRC remainder calculated by the CRC_CALCULATE command is all zeros FLG_EQ0 asserted when all fl ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller COMMAND CRC_RECALCULATE Calculate CRC remainder buffer data, storing result in ECC RAM and updating microprocessor status bit CRC_EQ0. Mode 2, Form 1 uses address 16 : 2075 2067; note 1 CALCULATE_SYNDROME Prepares buffer for correction, calculates P and Q syndromes, and copies error flags S and CRC remainder from buffer to ECC RAM ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 8.3 Microprocessor interrupts An interrupts pulse is generated upon completion of any of the following commands: CALCULATE_SYNDROMES (not Mode 2, Form 1) CALCULATE_SYNDROMES (Mode 2, Form 1) CRC_RECALCULATE (not Mode 2, Form 1) CRC_RECALCULATE (Mode 2, Form 1) COPY_RESULTS (not Mode 2, Form 1) COPY_RESULTS (Mode 2, Form 1) CORRECT_P_SYNDROMES CORRECT_Q_SYNDROMES ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller bit location in INTRFLG will clear the corresponding interrupt masked interrupt occurs, the microcontroller can still detect the occurrence because the event is still posted in INTRFLG. Table 8 Interrupt mask register: 0xF0FB MNEMONIC R/W 7 INTRMSK R/W MASK7 Each bit in register 0xF0FB corresponds to the interrupt at the same bit location in register 0xF0FC. To enable an interrupt, the bit in this register must be set HIGH. Table 9 Interrupt fl ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 11 Microcontroller frame number address registers: 0xF0F6 and 0xF0F7; note 1 MNEMONIC R/W 7 MICFRM# R/W FRAME7 MICFRM# R/W Note 1. Registers 0xF0F6 and 0xF0F7 provide the frame number address for the microcontroller access to memory. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, halfpage Table 13 SAA7390 address map details for the 80C32 ADDRESS 0000 to 7FFF This 32 kbytes window is used to address and portion the DRAM buffer intended for non-frame mapped memory to be addressed through this window. The upper page address bits (to address the full range of the DRAM buffer) are set by the linear address page register (PAGEREG) ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 9 FRONT PANEL AND MISCELLANEOUS CONTROL SIGNALS This Chapter describes the various SAA7390 control signals; front panel and basic engine signals, jumper settings and use of the general purpose signals. Table 14 Start clock doubler: 0xF091 MNEMONIC ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 18 RDSW field descriptions FIELD LOGIC TRAYSW 0 tray position in 1 tray position out EJECT user is requesting the drive tray to open (active LOW) VOLDN user is requesting a decrease in volume (active LOW) VOLUP user is requesting an increase in volume (active LOW) HFD high frequency detection ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 22 GPIOCTL field descriptions FIELD GPDIR1 General purpose bit direction control. Default LOW puts GPIO1 into the input mode, setting this HIGH puts GPIO1 in output mode. GPDAT1 GPIO1 data bit. GPDIR2 General purpose bit direction control. Default LOW puts GPIO2 into the input mode, setting this HIGH puts GPIO2 in output mode ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 25 Baud rate generator control: 0xF0C0; note 1 MNEMONIC R/W 7 BRGSEL R/W C_34_16 Note 1. Register 0xF0C0 controls the S2B UART baud rate and selective inversion of the sub-code information. Control over the parity and the clock doubler is also included together with the ability to invert the sub-code and Q-channel information. Table 26 BRGSEL fi ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 28 UARTCTL field descriptions FIELD CSD_SEL elects COM_SYNC falling edge when set CSU_SEL selects COM_SYNC rising edge when set SSD_SEL selects SYS_SYNC falling edge when set SSU_SEL selects SYS_SYNC rising edge when set CSD_REP ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 31 Track descriptor block address: 0xF096 and 0xF097; note 1 MNEMONIC R/W 7 TDB R/W TDB R/W Note 1. Registers 0xF096 and 0xF097 contain the frame address of the TDB. When the buffer manager frame count equals the contents of this register and the TDB_EN bit is set in BMFECTL, the frame counter will not be allowed to increment until TDB_CNT equals zero ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 34 SCSI mode control register: 0xF0FD; note 1 MNEMONIC R/W 7 HOSTMOD R/W Note 1. Register 0xF0FD controls the operation of the interface to the host interface controller. The outputs of these registers are used to directly control DRAM access cycles, and will affect any current DRAM cycle in progress. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 37 Q-channel information: 0xF084, F094, F095, F0A9, F0AA, F0AB, F0B1, F0B2, F0CF and F0FA,; note 1 MNEMONIC R/W 7 QZERO R QTNO R QINDX R QMODE R QAMIN R QASEC R QAFRM R QMIN R QSEC R QFRM R Note 1. These registers contain the information taken from the raw sub-channel information from the CD decoder. Due to the fact that this data has not had any error correction applied to it necessary to perform a CRC check for validity. Twelve bytes of Q-channel information are assembled from each sector of data ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 10.2 Front-end status and control Table 39 Front-end control: 0xF0BB; note 1 MNEMONIC R/W 7 FECTL R/W SIM_EOF Note 1. Register 0xF0BB controls the front-end of the SAA7390. The naming convention used here is similar to that used in the block decoders. Table 40 FECTL field descriptions ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 41 Read status register: 0xF0C3; note 1 MNEMONIC R/W 7 RDDSTAT R DCOTACT Note 1. The information in register 0xF0C3 is a copy of the status byte written to the data buffer at the end of every frame. SYNCERR, DATERR and CRCERR are essentially unusable since they are valid only long enough to be written to the buffer. Table 42 RDDSTAT fi ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 11 BUFFER MANAGER 11.1 Front-end to buffer manager interface The buffer manager interface to the front-end is write only with no handshaking. The front-end passes one byte of data and a write strobe to the buffer manager; this byte will be one of five types of data (see Table 44). The data byte is latched and the interface is given the highest priority thus no wait signal is required ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 44 Front-end frame offset: 0xF0E2, F0E3; note 1 MNEMONIC R/W 7 FEFRMOFF R/W FEFRMOFF R/W Note 1. This register allows the front-end frame offset counter to be read and reloaded. The counter associated with these registers is loaded after the most significant byte is written; the least significant byte must be written first to ensure that the counter is loaded correctly ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 48 Buffer manager front-end control: 0xF0E1 MNEMONIC R/W 7 BMFECTL R/W Table 49 BMFECTL field descriptions FIELD LOGIC TDB_EN Track Descriptor Block (TDB) enable; default LOW. When set, this causes the buffer manager to continuously output the frame addressed by TBDL/TDBH for as many frames as programmed into TDB_CNT ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 50 Last complete frame number: 0xF0E6, F0E7; note 1 MNEMONIC R/W 7 LSTCMPFM R FRAME7 LSTCMPFM R Note 1. This register provides the address of the last complete frame that was received. 11.3 ECC to buffer manager interface The ECC logic is able to access the buffer manager frame memory in either byte or burst mode. The ECC logic provides an offset address and uses a frame address programmed by the microcontroller, ECCFRM# ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller The transfer block is specified by registers HOSTOFFS and HOSTOFFE. For each frame, the transfer will start at the address specified by HOSTOFFS and continue until the address specified by HOSTOFFE is transferred. After each block is transferred, the frame address HOSTCFRM will be incremented and the transfer will continue with the same address block from the next frame ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 53 Host interface offset start register (A and B): 0xF0E8, F0E9; note 1 MNEMONIC R/W 7 HOSTOFFS R/W HOSTOFFS R/W Note 1. These registers, together with the offset end registers, allow full control over the number of frame bytes that will be transferred to the host interface port. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 57 Ending frame number: 0xF0F2, F0F3 MNEMONIC R/W 7 LSTFHOST R/W FRAME7 LSTFHOST R/W 11.5 Miscellaneous buffer manager considerations The following bandwidth limitation must be observed in normal operation: Only 833 ns is available between each data write from the front-end at the maximum 8 times transfer rate. At the end of the frame, multiple front-end writes may stack up, so the microcontroller accesses to DRAM will be off (PCLK stopped) during the end of frame time ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 60 Automatic start and stop control functions (same address): 0xF0C5, F0C6 and F0C7 MNEMONIC R/W 7 STRTMIN R/W STRTSEC R/W STRTFRM R/W STOPCNT R/W STOPCNT R/W The multiplexing between the start and stop registers is achieved by programming STOP in BMFECTL. If STOP is clear then STRTMIN, STRTSEC and STRTFRM are accessible, otherwise STOPCNT may be accessed ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller microcontroller handbook, full pagewidth access MICROCONTROLLER INTERFACE BLOCK COUNTER AND HEADER GENERATION DATA INTERFACE data cource handbook, full pagewidth MICROCONTROLLER INTERFACE Fig.14 Generation of the header and sub-header information. 1996 Jul 02 ROM RAM ERROR CORRECTION ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 61 Interrupt mask register: 0xF0CE; note 1 MNEMONIC R/W 7 CMSK R/W Note 1. Register 0xF0CE contains the mask bits for the various SAA7390 specific interrupts. Setting a mask bit HIGH enables the interrupt. The register is cleared to all zeros after reset. The definitions of the bit fields of CMSK are given in Table .63. Table 62 CMSK fi ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 64 CCMD field descriptions FIELD LOGIC ED2 0 no EDC in CDI, Form 2; zeros replace CRC; note 1 1 EDC is performed in CDI, Form 2; note 1 SBH 0 sub-header retrieved from sub-header register; note 2 1 sub-header retrieved from host data; note 2 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 66 CSTS field descriptions FIELD LOGIC SAR 0 status not ready yet during this block; SAR cleared on each new block 1 status already read (1) NRQ 0 no request to host will be issued 1 requests to host will be issued (2) RDY 0 data block transmission is in progress ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Automatic header generation is implemented in the CDB2. Once the initial header value is loaded, the header is incremented and added to the user data in accordance with the Yellow book rules. When the information is written into the header registers, this is used by the CDB2 at the start of the next frame. MODE1 and MODE0 specifies the CD-ROM mode used, even when NHD = logic 1. Table 69 Sub-header information fi ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller Table 72 CCTL field descriptions FIELD LOGIC RSTA to reset CDB2, first set RSTA HIGH then LOW CDB2ECC when set, enables the ECC RAM to be used by the CDB2 during encoding of ECC parity (1) HSH 0 header supplied from CDB2 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 12 FRAME BUFFER ORGANIZATION The break-down of the 3 kbytes frame buffer is described in this section. Table 75 Frame buffer organization DECIMAL START END 2063 2064 2067 2068 2075 2076 2247 2248 2351 2352 2367 2368 2463 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 13 SUMMARY OF CONTROL REGISTER MAP Table 77 Control register map for the SAA7390 ADDRESS MNEMONIC F084 QZERO F085 ECCCTL F086 ECCSTAT F08E NUM_COR F08F TDB_CNT F091 CLKSEL F092 HDRMODE F093 HDRFRM F094 QFRM F095 QMIN F096 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller ADDRESS MNEMONIC F0B7 HOSTPASS F0B9 WTGCTL F0BA RDSW F0BB FECTL F0BC HOSTPASS F0BD HOSTPASS F0BE HOSTPASS F0BF HOSTPASS F0C0 BRGSEL F0C1 WTDIR F0C2 GPIOCTL F0C3 RDDSTAT F0C4 SERCOM F0C5 STRTMIN F0C6 STRTSEC F0C6 STOPCNT ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller ADDRESS MNEMONIC F0E6 LSTCMPFM F0E7 LSTCMPFM F0E8 HOSTOFFS F0E9 HOSTOFFS F0EA HOSTOFFE F0EB HOSTOFFE F0EC HOSTSFRM F0ED HOSTSFRM F0EE HOSTCFRM F0EF HOSTCFRM F0F1 SC_CTL F0F2 LSTFHOST F0F3 LSTFHOST F0F4 ECCFRM# F0F5 ECCFRM# F0F6 MICFRM# ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 14 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL V digital supply voltage DD V maximum input voltage on any pin i(max) V output voltage on any output o T storage temperature stg 15 OPERATING CHARACTERISTICS 2 15.1 I S-bus timing; data mode V = 4.75 to 5.25 V ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.2 EIAJ timing; audio mode V = 4. SYMBOL PARAMETER EIAJ timing (single speed n); see Fig.16 and note CLAB LOCK INPUT T output clock period cy t clock HIGH time CH t clock LOW time DAAB, WSAB ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth CLAB DAAB 1 WSAB left LSB valid EFAB (error flags) CLAB DAAB WSAB EFAB CLAB handbook, full pagewidth DAAB 1 0 WSAB EFAB CLAB DAAB WSAB EFAB 1996 Jul ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.3 R-W timing (see Fig.17) The data from sub-code R-W may be read via the V4 pin from the CD-decoder (SAA7372) and has a format similar to RS232. The sub-code synchronization word is formatted by a pause of 200 s minimum. Each sub-code byte starts with a logic 1 followed by seven bits (Q to W). ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.5 S2B interface timing The S2B serial interface consists of four lines (see Fig.19): Transmit data (TXD) Receive data (RXD) Data path ready to accept data; active LOW (CPR) Basic engine ready to accept data; active LOW (SPR). ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.6 SPI interface timing The control communication between the CD-R engine and the interface module is based on data blocks that are swapped in the same cycle. The control communication channel is byte and message synchronous. Byte synchronization is realized with an acknowledge after each byte that is transferred ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth serial data in acknowledge handbook, full pagewidth COM_CLK COM_IN COM_OUT Fig.23 Synchronous serial communication channel timing. 1996 Jul 700 30 to 700 s s Fig.22 Acknowledge signal timing Preliminary specifi ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.6.1 R ELATIONSHIP BETWEEN COMMUNICATION AND SYSTEM SYNCHRONIZATION The system synchronization line (SYS_SYNC) is locked on a hardware generated frame synchronization; the decoders sub-code, the ATIP and the encoders synchronization signals. The communication synchronization line (COM_SYNC) has the same frequency as SYS_SYNC, except for four-times speed operation, where it is down-scaled with a factor 3. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.7 Microprocessor interface V = 4. SYMBOL Microprocessor timing; see Figs 26, 27 and 28 t ALE pulse width LHLL t address valid to ALE LOW AVLL t address hold after ALE LOW LLAX t ALE LOW to PSEN LOW LLPL ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth PSEN LA7 to LA0 A15 to A8 handbook, full pagewidth ALE PSEN UC_RD UC_AD7 to UC_AD0 UC_A15 to UC_A8 1996 Jul 02 t LHLL ALE t AVLL t LLPL t LLAX t PLAZ t AVIV Fig.26 External program memory read cycle. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth ALE PSEN UC_WR UC_AD7 to UC_AD0 UC_A15 to UC_A8 1996 Jul 02 t LLWL t RLRH t LLAX t AVLL t QVWX t AVWL Fig.28 External data memory write cycle. 62 Preliminary specification t WHLH t WHQX MGE530 SAA7390 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.8 Host interface 15.8.1 R EGISTER INTERFACE V = 4. SYMBOL Read cycle timing; see Fig.29; note 1 t address set-up time to HOSTSEL LOW 1 t address hold time from HOSTSEL LOW 2 t HOSTSEL HIGH to HOSTSEL LOW 3 t HOSTSEL LOW to HOSTRD LOW ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller UC_AD3 handbook, full pagewidth to UC_AD0 HOSTSEL HOSTRD UC_AD7 to UC_AD0 UC_AD3 handbook, full pagewidth to UC_AD0 HOSTSEL HOSTWR UC_AD7 to UC_AD0 1996 Jul Fig.29 Register read cycle timing ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.8.2 DMA INTERFACE TIMING V = 4. SYMBOL DMA read cycle timing; see Fig.31 t DACK LOW to DREQ LOW 1 t DACK HIGH to DREQ HIGH 2 t DACK HIGH to DACK LOW 3 t DACK pulse width 4 t DACK LOW to DACK LOW ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller dbook, full pagewidth DREQ DACK HOSTRD SD7 to SD0 handbook, full pagewidth DREQ DACK HOSTWR SD7 to SD0 1996 Jul Fig.31 DMA read cycle timing. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 15.9 DRAM interface (the SAA7390 is designed to operate with standard 70 ns DRAMs 4. SYMBOL DRAM interface timing; see Figs access time from column address acc;CA t column address hold time from RAS hCA ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller SYMBOL t write command to RAS lead time RASL;W t transition time (rise or fall) trans t write command hold time hW t write command hold time (referenced to RAS) hW;RAS t WE command set-up time su;WE t write command pulse width W hold time (CBR refresh) h ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth RAS t pCAS;RAS CAS t su;RA ADDRESS ROW DATA 1996 Jul 02 t cy;R/W t W;RAS t h;CAS t h;RAS t dRAS;CAS t W;CAS t hCA;RAS t dRAS;CA t h;RA t su;CA t h;CA COLUMN t hDAT;RAS t su;DAT t h;DAT Fig.34 DRAM early write cycle. 69 Preliminary specification t pRAS t CA;RASL ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller andbook, full pagewidth 1996 Jul 02 70 Preliminary specification SAA7390 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller andbook, full pagewidth 1996 Jul 02 71 Preliminary specification SAA7390 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller handbook, full pagewidth ADDRESS 1996 Jul 02 t cy;R/W t W;RAS RAS t pCAS;RAS CAS t su;RA t h;RA ROW Fig.37 DRAM refresh cycle. 72 Preliminary specification t pRAS t pRAS;CAS ROW MGE416 SAA7390 ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 16 PACKAGE OUTLINE SQFP128: plastic shrink quad flat package; 128 leads (lead length 1.6 mm); body 2 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions UNIT max. min. 3.05 mm 3.40 0.25 0.25 2.55 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 17 SOLDERING 17.1 Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities ...

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... Philips Semiconductors High performance Compact Disc-Recordable (CD-R) controller 18 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains fi ...

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... Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +1 800 234 7381, Fax. +1 708 296 8556 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. + 24825 © Philips Electronics N.V. 1996 All rights are reserved ...

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