XC3030L Xilinx, XC3030L Datasheet - Page 11

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Figure 9. LCA General-Purpose Interconnect.
Composed of a grid of metal segments that may be intercon-
nected through switch matrices to form networks for CLB and
IOB inputs and outputs.
Figure 10. Switch Matrix Interconnection Options for Each
Pin. Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT system
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Figure 11. CLB X and Y Outputs.
The X and Y outputs of each CLB have single contact, direct
access to inputs of adjacent CLBs
Special buffers within the general interconnect areas pro-
vide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices,
above and to the right and may be highlighted by the use
of the Show BIDI command in the XACT system. The other
PIPs adjacent to the matrices are accessed to or from
Longlines. The development system automatically de-
fines the buffer direction based on the location of the
interconnection network source. The delay calculator of
the XACT development system automatically calculates
and displays the block, interconnect and buffer delays for
any paths selected. Generation of the simulation netlist
with a worst-case delay model is provided by an XACT
option.
Direct Interconnect
Direct interconnect, shown in Figure 11, provides the most
efficient implementation of networks between adjacent
CLBs or I/O Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the B input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct
interconnect to drive the D input of the block immediately
above and the A input of the block below. Direct intercon-
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