XC3030L Xilinx, XC3030L Datasheet - Page 14

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND func-
tion. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the Longline Low. See Figure
15b. Pull-up resistors are available at each end of the
Figure 14. Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers
allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines
per column (except XC3020) and the outer perimeter Longlines may be programmed as connectible half-length lines.
Figure 15a. 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state
lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer
inputs are driven by the control signals or a Low.
Figure 15b. 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
V
CC
KEEPER
CIRCUIT
D
WEAK
A
D
A
A
D
B
D
B
B
Z
=
D
2-116
Z = D
A
•
A
A
+
• D
D
Longline to provide a High output when all connected
buffers are non-conducting. This forms fast, wide gating
functions. When data drives the inputs, and separate
signals drive the 3-state control lines, these buffers form
multiplexers (3-state busses). In this case, care must be
used to prevent contention through multiple active buffers
C
D
B
B
• D
•
D
B
C
C
C
•
+ D
...
• D
C
N
•
C
+
… +
D
N
•
N
D
(LOW)
D
N
N
N
T
X3036
V
CC
OE
X1741
X1244