XC3030L Xilinx, XC3030L Datasheet - Page 16

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Figure 17. Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an output network for its buffer,
the crystal oscillator inverter uses two unconfigured package pins and external components to implement an oscillator. An optional
divide-by-two mode is available to assure symmetry.
Table 1
resistance. Crystal oscillators above 20 MHz generally
require a crystal which operates in a third overtone mode,
where the fundamental frequency must be suppressed by
an inductor across C2, turning this parallel resonant circuit
to double the fundamental crystal frequency, i.e., 2/3 of the
desired third harmonic frequency network. When the oscil-
lator inverter is not used, these IOBs and their package
pins are available for general user I/O.
Programming
M0 M1 M2 CCLK
0
0
0
0
1
1
1
1
0 0 output
0 1 output
1 0 —
1 1 output
0 0 —
0 1 output
1 0 —
1 1 input
C1, C2
Suggested Component Values
XTAL 1 (OUT)
XTAL 2 (IN)
R1
R2
Y1
Master
Master
reserved
Master
reserved
Peripheral Byte Wide
reserved
Slave
Mode
0.5 – 1 M
0 – 1 k
(may be required for low frequency, phase)t
(shift and/or compensation level for crystal Q)
10 – 40 pF
1 – 20 MHz AT-cut parallel resonant
44 PIN
PLCC
30
26
Bit Serial
Byte Wide Addr. = 0000 up
—
Byte Wide Addr. = FFFF
down
—
—
Bit Serial
68 PIN
PLCC
Data
D
47
43
Clock Buffer
Q
Alternate
PLCC
57
53
84 PIN
PGA
L11
J11
CQFP
67
61
2-118
XTAL2
100 PIN
(IN)
PQFP
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vcc reaches the voltage at which portions
of the LCA device begin to operate (nominally 2.5 to 3 V),
the programmable I/O output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power
supply voltage to stabilize. During this time the power-
down mode is inhibited. The Initialization state time-out
(about 11 to 33 ms) is determined by a 14-bit counter
driven by a self-generated internal timer. This nominal 1-
MHz timer is subject to variations with process, tempera-
ture and power supply. As shown in Table 1, five configu-
ration mode choices are available as determined by the
input levels of three mode pins; M0, M1 and M2.
In Master configuration modes, the LCA device becomes
the source of the Configuration Clock (CCLK). The begin-
ning of configuration of devices using Peripheral or Slave
modes must be delayed long enough for their initialization
to be completed. An LCA device with mode lines selecting
a Master configuration mode extends its initialization state
using four times the delay (43 to 130 ms) to assure that all
daisy-chained slave devices, which it may be driving, will
82
76
C1
132 PIN
PGA
M13
P13
Y1
160 PIN
PQFP
82
76
XTAL1
Internal
164 PIN
C2
CQFP
105
99
External
175 PIN
R1
R2
PGA
T14
P15
208 PIN
PQFP
110
100
X5302