XC3030L Xilinx, XC3030L Datasheet - Page 18

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Clear or Configure states. They and DONE/PROG provide
signals for control of external logic signals such as RESET,
bus enable or PROM enable during configuration. For
parallel Master configuration modes, these signals pro-
vide PROM enable control and allow the data pins to be
shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs
have TTL thresholds and can change to CMOS thresholds
Figure 19. Internal Configuration Data Structure for an LCA Device. This shows the preamble, length count and data frames
generated by the XACT Development System.
The Length Count produced by the MakeBits program = [(40-bit preamble + sum of program data + 1 per daisy chain device)
rounded up to multiple of 8] – (2
if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is reached.
Device
Gates
CLBs
Row x Col
IOBs
Flip-flops
Horizontal Longlines 16
TBUFs/Horizontal LL 9
Bits per Frame
(including1 start and 3 stop bits)
Frames
Program Data =
Bits x Frames + 4 bits
(excludes header)
PROM size (bits) =
Program Data
+ 40-bit Header
11111111
0010
< 24-Bit Length Count >
1111
0 <Data Frame # 001 > 111
0 <Data Frame # 002 > 111
0 <Data Frame # 003 > 111
0 <Data Frame # 196 > 111
0 <Data Frame # 197 > 111
1111
.
.
.
.
*The LCA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits
.
.
.
.
K
.
.
.
.
4) where K is a function of DONE and RESET timing selected. An additional 8 is added
XC3020
XC3020A
XC3020L
XC3120
XC3120A
1,000 to
1,500
64
(8 x 8)
64
256
75
197
14,779
14,819
XC3030
XC3030A
XC3030L
XC3130
XC3130A
1,500 to
2,000
100
(10 x 10)
80
360
20
11
92
241
22,176
22,216
—Dummy Bits*
—Preamble Code
—Configuration Program Length
—Dummy Bits (4 Bits Minimum)
Postamble Code (4 Bits Minimum)
2-120
XC3042
XC3042A
XC3042L
XC3142
XC3142A
2,000 to
3,000
144
(12 x 12)
96
480
24
13
108
285
30,784
30,824
For XC3120
197 Configuration Data Frames
(Each Frame Consists of:
at the completion of configuration if the user has selected
CMOS thresholds. The threshold of PWRDWN and the
direct clock inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.
Configuration Data
Configuration data to define the function and interconnec-
tion within a Logic Cell Array is loaded from an external
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits
XC3064
XC3064A
XC3064L
XC3164
XC3164A
3,500 to
4,500
224
(16 x 14)
120
688
32
15
140
329
46,064
46,104
XC3090
XC3090A
XC3090L
XC3190
XC3190A
5,000 to
6,000
320
(20 x 16)
144
928
40
17
172
373
64,160
64,200
Header
Program Data
Repeated for Each Logic
Cell Array in a Daisy Chain
XC3195
XC3195A
6,500 to
7,500
484
(22 x 22)
176
1,320
44
23
188
505
94,944
94,984
X5300