XC3030L Xilinx, XC3030L Datasheet - Page 19

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

storage at power-up and after a re-program signal. Several
methods of automatic and controlled loading of the re-
quired data are available. Logic levels applied to mode
selection pins at the start of configuration time determine
the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configu-
ration mode. The different LCA devices have different
sizes and numbers of data frames. To maintain compatibil-
ity between various device types, the Xilinx product fami-
lies use compatible configuration formats. For the
XC3020, configuration requires 14779 bits for each de-
vice, arranged in 197 data frames. An additional 40 bits are
used in the header. See Figure 20. The specific data
format for each device is produced by the MakeBits
command of the development system and one or more of
these files can then be combined and appended to a length
count preamble and be transformed into a PROM format
file by the MakePROM command of the XACT develop-
ment system. A compatibility exception precludes the use
of an XC2000-series device as the master for XC3000-
series devices if their DONE or RESET are programmed
to occur after their outputs become active.
The Tie Option of the MakeBits program defines output
levels of unused blocks of a design and connects these to
unused routing resources. This prevents indeterminate
levels that might produce parasitic supply currents. If
unused blocks are not sufficient to complete the tie, the
Figure 20. Configuration and Start-up of One or More LCA Devices.
DIN
*
The configuration data consists of a composite
40-bit preamble/length count, followed by one or
more concatenated LCA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.
Heavy lines indicate the default condition
Preamble
12
Length Count
24
4
Start
Bit
Data Frame
2-121
Data
Flagnet command of EDITLCA can be used to indicate
nets which must not be used to drive the remaining unused
routing, as that might affect timing of user nets. Norestore
will retain the results of tie for timing analysis with Querynet
before Restore returns the design to the untied condition.
Tie can be omitted for quick breadboard iterations where
a few additional milliamps of I
The configuration bitstream begins with eight High pre-
amble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the LCA device
is set to zero and begins to count the total number of
configuration clock cycles applied to the device. As each
configuration data frame is supplied to the LCA device, it is
internally assembled into a data word, which is then loaded
in parallel into one word of the internal configuration
memory array. The configuration loading process is com-
plete when the current length count equals the loaded
length count and the required configuration program data
frames have been written. Internal user flip-flops are held
Reset during configuration.
Two user-programmable pins are defined in the unconfig-
ured Logic Cell array. High During Configuration (HDC)
and Low During Configuration (LDC) as well as
DONE/PROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Stop
3
Start
Bit
Last Frame
Length Count*
Internal Reset
Weak Pull-Up
STOP
PROGRAM
CC
3
Postamble
are acceptable.
4
I/O Active
DONE
X5303