XC3030L Xilinx, XC3030L Datasheet - Page 20

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Enable. After the last configuration data bit is loaded and
the length count compares, the user I/O pins become
active. Options in the MakeBits program allow timing
choices of one clock earlier or later for the timing of the end
of the internal logic RESET and the assertion of the DONE
signal. The open-drain DONE/PROG output can be AND-
tied with multiple LCA devices and used as an active-High
READY, an active-Low PROM enable or a RESET to other
portions of the system. The state diagram of Figure 18
illustrates the configuration process.
Master Mode
In Master mode, the LCA device automatically loads
configuration data from an external memory device. There
are three Master modes that use the internal timing source
to supply the configuration clock (CCLK) to time the
incoming data. Master Serial mode uses serial configura-
tion data supplied to Data-in (DIN) from a synchronous
serial source such as the Xilinx Serial Configuration PROM
shown in Figure 21. Master Parallel Low and High modes
automatically use parallel data supplied to the D0–D7 pins
in response to the 16-bit address generated by the LCA
device. Figure 22 shows an example of the parallel Master
mode connections required. The LCA HEX starting ad-
dress is 0000 and increments for Master Low mode and it
is FFFF and decrements for Master High mode. These two
modes provide address compatibility with microproces-
sors which begin execution from opposite ends of memory.
Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, as a processor
peripheral. Figure 23 shows the peripheral mode connec-
tions. Processor write cycles are decoded from the com-
mon assertion of the active low Write Strobe (WS), and two
active low and one active high Chip Selects (CS0, CS1,
CS2). The LCA device generates a configuration clock
from the internal timing generator and serializes the paral-
lel input data for internal framing or for succeeding slaves
on Data Out (DOUT). A output High on READY/BUSY pin
indicates the completion of loading for each byte when the
input register is ready for a new byte. As with Master
modes, Peripheral mode may also be used as a lead
device for a daisy-chain of slave devices.
Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Logic Cell Array configuration as shown in Figure 24.
Serial data is supplied in conjunction with a synchronizing
input clock. Most Slave mode applications are in daisy-
chain configurations in which the data input is driven from
the previous Logic Cell Array’s data out, while the clock is
supplied by a lead device in Master or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.
2-122
Daisy Chain
The XACT development system is used to create a com-
posite configuration for selected LCA devices including: a
preamble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a pos-
sible daisy-chain, a lead device will load its configuration
data frames while providing a High DOUT to possible
down-stream devices as shown in Figure 22. Loading
continues while the lead device has received its configura-
tion program and the current length count has not reached
the full value. The additional data is passed through the
lead device and appears on the Data Out (DOUT) pin in
serial form. The lead device also generates the Configura-
tion Clock (CCLK) to synchronize the serial output data
and data in of down-stream LCA devices. Data is read in
on DIN of slave devices by the positive edge of CCLK
and shifted out the DOUT on the negative edge of CCLK.
A parallel Master mode device uses its internal timing
generator to produce an internal CCLK of 8 times its
EPROM address rate, while a Peripheral mode device
produces a burst of 8 CCLKs for each chip select and write-
strobe cycle. The internal timing generator continues to
operate for general timing and synchronization of inputs in
all modes.
Special Configuration Functions
The configuration data includes control over several spe-
cial functions in addition to the normal user logic functions
and interconnect.
• Input thresholds
• Readback disable
• DONE pull-up resistor
• DONE timing
• RESET timing
• Oscillator frequency divided by two
Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACT
development system bitstream generation process.
Input Thresholds
Prior to the completion of configuration all LCA device
input thresholds are TTL compatible. Upon completion of
configuration, the input thresholds become either TTL or
CMOS compatible as programmed. The use of the TTL
threshold option requires some additional supply current
for threshold shifting. The exception is the threshold of the
PWRDWN input and direct clocks which always have a
CMOS input. Prior to the completion of configuration the
user I/O pins each have a high impedance pull-up. The