XC3030L Xilinx, XC3030L Datasheet - Page 22

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its DOUT
pin. There is an internal delay of 1.5 CCLK periods, which
Figure 21. Master Serial Mode
RESISTOR OVERCOMES THE
DURING CONFIGURATION
THE 5 k M2 PULL-DOWN
BUT IT ALLOWS M2 TO
INTERNAL PULL-UP,
5-k RESISTOR IS
*
SERIES WITH M1
IF READBACK IS
ACTIVATED, A
REQUIRED IN
BE USER I/O.
GENERAL-
PURPOSE
USER I/O
RESET
PINS
•
•
•
•
•
DOUT
M2
HDC
RESET
LDC
INIT
M0
OTHER
I/O PINS
*
M1
XC3000
DEVICE
LCA
PWRDWN
(LOW RESETS THE XC17xx ADDRESS POINTER)
+5 V
2-124
CCLK
DIN
D/P
INIT
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE . Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
DATA
CLK
CE
OE/RESET
+5 V
V CC
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
XC17xx
SCP
V PP
CEO
CE
OE/RESET
DATA
CLK
CASCADED
MEMORY
SERIAL
X6092