XC3030L Xilinx, XC3030L Datasheet - Page 23

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Master Serial Mode Programming Switching Characteristics
Notes: 1. At power-up, V
CCLK
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
3. Master-serial-mode timing is based on slave-mode testing.
delayed by holding RESET Low until V
>100 ms, or a non-monotonically rising V
level on RESET and D/P after V
devices is High.
Serial Data In
Serial DOUT
(Output)
(Output)
CCLK
CC
must rise from 2.0 V to V
Description
Data In setup
Data In hold
n – 3
1
T
DSCK
n
CC
has reached 4.0 V (2.5 V for the XC3000L).
Speed Grade
CC
CC
n – 2
has reached 4.0 V (2.5 V for the XC3000L). A very long V
CC
may require >6- s High level on RESET, followed by a >6- s Low
min in less than 25 ms. If this is not possible, configuration can be
1 T
2
2 T
Symbol
2-125
CKDS
CKDS
n + 1
DSCK
n – 1
n + 2
Min
60
0
n
Max
CC
X3223
rise time of
Units
ns
ns