XC3030L Xilinx, XC3030L Datasheet - Page 28

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Slave Serial Mode
Figure 24. Slave Serial Mode.
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
RESET
Computer
Micro
Port
I/O
STRB
D0
D1
D2
D3
D4
D5
D6
D7
+5 V
+5 V
2-130
CCLK
DIN
INIT
RESET
M0
data (and all data that overflows the lead device) on its
DOUT pin. There is an internal delay of 0.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next LCA device in the daisy-chain accepts
data on the subsequent rising CCLK edge.
D/P
*
M1
LCA
PWRDWN
I/O Pins
Other
DOUT
HDC
LDC
M2
5 kΩ
General-
Purpose
User I/O
Pins
*
Optional
Daisy-Chained
LCAs with
Different
Configurations
If Readback is
Activated, a
5-kΩ Resistor is
Required in
Series with M1
X3157