XC3030L Xilinx, XC3030L Datasheet - Page 29

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

Slave Serial Mode Programming Switching Characteristics
Notes: 1. The max limit of CCLK Low time is caused by dynamic circuitry inside the LCA device.
Program Readback Switching Characteristics
Notes: 1. During Readback, CCLK frequency may not exceed 1 MHz.
CCLK
RTRIG
CCLK
2. Configuration must be delayed until the INIT of all LCA devices is High.
3. At power-up, V
2. RETRIG (M0 positive transition) shall not be done until after one clock following active I/O pins.
3. Readback should not be initiated until configuration is complete.
4. T
(Output)
layed by holding RESET Low until V
ms, or a non-monotonically rising V
RESET and D/P after V
DOUT
CCLK
CCLR
DIN
RDATA Output
DONE/PROG
RTRIG (M0)
is 5 s min to 15 s max for XC3000L.
(OUTPUT)
M1 Input/
CCLK(1)
CC
must rise from 2.0 V to V
Description
To DOUT
DIN setup
DIN hold
High time
Low time (Note 1)
Frequency
Description
RTRIG High
RTRIG setup
RDATA delay
High time
Low time
1 T
CC
DCC
3
has reached 4.0 V (2.5 V for the XC3000L).
H1-Z
T
CCRD
Bit n
4
T
CCL
2 T
CC
CC
CCD
may require a >6- s High level on RESET, followed by a >6- s Low level on
1 T
has reached 4.0 V (2.5 V for the XC3000L). A very long V
2
Bit n - 1
RTH
4 T
CC
T
RTCC
5
CCH
min in less than 25 ms. If this is not possible, configuration can be de-
READBACK OUTPUT
2-131
3
1
2
4
5
1
2
3
5
4
Symbol
VALID
Symbol
Bit n + 1
4
T
T
T
T
T
F
T
T
T
T
T
T
CCO
DCC
CCD
CCH
CCL
CC
CCL
RTH
RTCC
CCRD
CCHR
CCLR
3 T
CCO
5 T
CCL
READBACK OUTPUT
0.05
0.05
Min
250
200
Min
0.5
0.5
60
0
VALID
X6116
Bit n
100
Max
5.0
10
Max
100
CC
5
X5379
rise time of >100
Units
MHz
ns
ns
ns
Units
s
s
ns
ns
ns
s
s