XC3030L Xilinx, XC3030L Datasheet - Page 33

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

One CLB driving three local interconnects
One global clock buffer and clock line
One device output with a 50 pF load
Power Consumption
The Logic Cell Array exhibits the low power consumption
characteristic of CMOS ICs. For any design, the configu-
ration option of TTL chip input threshold requires power for
the threshold reference. The power required by the static
memory cells that hold the configuration data is very low
and may be maintained in a power-down mode.
Typically, most of power dissipation is produced by exter-
nal capacitive loads on the output buffers. This load and
frequency dependent power is 25 W/pF/MHz per output.
Another component of I/O power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an LCA device, the fraction of nodes changing on a
given clock is typically low (10-20%). For example, in a
long binary counter, the total activity of all counter flip-flops
is equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is be-
tween 2.0 mW/MHz for the XC3020 and 3.5 mW/MHz for
the XC3090. The internal capacitive load is more a func-
tion of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the Logic Cell Array is
CMOS static memory, its cells require a very low standby
current for data retention. In some systems, this low data
retention current characteristic can be used as a method
of preserving configurations in the event of a primary
Dynamic Power Consumption
XC3042
0.25
2.25
1.25
2-135
power loss. The Logic Cell Array has built in Powerdown
logic which, when activated, will disable normal operation
of the device and retain only the configuration data. All
internal operation is suspended and output buffers are
placed in their high-impedance state with no pull-ups.
Different from the XC3000 family which can be powered
down to a current consumption of a few microamps, the
XC3100 draws 5 mA, even in power-down. This makes
power-down operation less meaningful. In contrast, I
for the XC3000L is only 10 A.
To force the Logic Cell Array into the Powerdown state, the
user must pull the PWRDWN pin Low and continue to
supply a retention voltage to the V
power is restored, V
voltage and PWRDWN is returned to a High. The Logic
Cell Array resumes operation with the same internal se-
quence that occurs at the conclusion of configuration.
Internal-I/O and logic-block storage elements will be reset,
the outputs will become enabled and the DONE/PROG
pin will be released.
When V
might unintentionally be supplied from an incoming signal
driving an I/O pin. The conventional electrostatic input
protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and
drive the V
invalid power conditions and should be avoided. A large
series resistor might be used to limit the current or a bipolar
buffer may be used to isolate the input signal.
XC3042A
0.17
1.40
1.25
CC
is shut down or disconnected, some power
CC
connection. This condition can produce
XC3042L
CC
0.07
0.50
0.55
is elevated to its normal operating
XC3142A
0.25
1.70
1.25
CC
pins. When normal
mW per MHz
mW per MHz
mW per MHz
CCPD