XC3030L Xilinx, XC3030L Datasheet - Page 36

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with
**** Pin assignments for the XC3195 PQ208 differ from those shown. See page 2-146.
*** Peripheral mode and master parallel mode are not supported in the PC44 package. See page 2-135.
(I) Represents an input
** Pin assignmnent for the XC3064/XC3090 and XC3195 differ from those shown. See page 2-138.
PWRDWN (I)
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
* INIT is an open drain output during configuration
LDC (LOW)
RESET (I)
CCLK (I)
<1:1:1>
SLAVE
DONE
DIN (I)
DOUT
GND
GND
VCC
INIT*
VCC
Represents a 50-k
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not electrically identical.
Generic I/O pins are not shown.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
For a detailed description of the configuration modes, see pages 2-190 through 2-200.
For pinout details, see pages 2-136 through 2-146.
MASTER-SER
PWRDWN (I)
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
RESET (I)
CCLK(O)
<0:0:0>
DONE
DIN (I)
DOUT
VCC
GND
VCC
GND
INIT*
Configuration Mode <M2:M1:M0>
to 100-k pull-up before and during configuration
PERIPHERAL
PWRDWN (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
M1 (LOW) (I)
HDC (HIGH)
LDC (LOW)
RDY/BUSY
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
RESET (I)
CCLK(O)
<1:0:1>
CS0 (I)
CS1 (I)
CS2 (I)
DONE
DOUT
WS (I)
GND
GND
VCC
VCC
INIT*
Pin Functions During Configuration
MASTER-HIGH
PWRDWN (I)
M1 (HIGH) (I)
M2 (HIGH) (I)
M0 (LOW) (I)
HDC (HIGH)
LDC (LOW)
RESET (I)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
CCLK(O)
a 50 k to 100 k pull-up resistor.
<1:1:0>
DONE
DOUT
RCLK
VCC
GND
VCC
GND
INIT*
A15
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
MASTER-LOW
PWRDWN (I)
M2 (HIGH) (I)
M1 (LOW) (I)
M0 (LOW) (I)
HDC (HIGH)
LDC (LOW)
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
DATA 0 (I)
RESET (I)
CCLK(O)
<1:0:0>
DONE
RCLK
DOUT
GND
GND
VCC
VCC
INIT*
A15
A14
A13
A12
A11
A10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
2-138
PLCC
***
44
12
16
17
18
19
20
22
23
26
27
28
30
34
38
39
40
X
7
1
PLCC
68
10
18
25
26
27
28
30
34
35
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
X
X
1
2
3
4
5
6
7
8
9
PLCC
X**
X**
X**
84
12
22
31
32
33
34
36
42
43
53
54
55
56
57
58
60
61
62
64
65
66
67
70
71
72
73
74
75
76
77
78
81
82
83
84
10
11
X
X
X
1
2
3
4
5
8
9
PGA
H10
G10
G11
D10
C11
C10
L11
K10
J10
K11
J11
F10
F11
E11
E10
B11
A11
B10
A10
84
B2
F3
K2
K3
K6
F9
B9
A9
B6
B7
A7
C7
C6
A6
A5
B5
C5
A3
A2
B3
A1
J2
L1
L3
J6
X
X
X
PQFP
100
100
29
41
52
54
56
57
59
65
66
76
78
80
81
82
83
87
88
89
91
92
93
94
98
99
12
13
14
15
16
17
18
19
20
23
24
25
26
X
X
X
1
2
5
6
8
9
TQFP
100
26
38
49
51
53
54
56
62
63
73
75
77
78
79
80
84
85
86
88
89
90
91
95
96
97
98
99
10
11
12
13
14
15
16
17
20
21
22
26
X
X
2
3
5
6
9
PGA
C13
D14
G14
H12
M13
N13
M12
N11
132
B13
A14
B14
P14
P13
M9
M8
M6
M5
M3
M2
A1
C8
N9
N8
N7
P6
N4
N2
P1
N1
K1
H1
H2
H3
G2
G1
F2
E1
D1
D2
B1
C2
L2
L1
J2
X
X
PQFP
160
159
100
102
103
108
114
115
119
120
121
124
125
128
129
132
133
136
137
139
141
142
147
148
151
152
155
156
20
40
42
44
45
49
59
19
76
78
80
81
82
86
92
93
98
X
X
PGA
175
B14
B15
C15
E14
D16
H15
P15
R15
R14
N13
T14
P12
T11
R10
J14
D9
R9
N9
R8
R7
R5
R3
N4
R2
M3
N1
M1
H2
H1
D1
C1
C2
B2
P8
P5
P2
P1
L2
K2
K1
F2
E1
E3
J3
X
X
PQFP
208
****
100
102
107
109
110
115
122
123
128
130
132
133
138
145
146
151
152
153
161
162
165
166
172
173
178
179
182
184
185
192
193
199
200
203
204
26
48
50
56
57
61
77
79
X
X
3
PROGRAM (I)
PWRDWN (I)
XTL2 OR I/O
XTL1 OR I/O
XC3020 etc.
XC3030 etc.
XC3042 etc.
XC3064 etc.
XC3090 etc.
RESET (I)
RTRIG (I)
All Others
Operation
CCLK (I)
XC3195
RDATA
VCC
GND
GND
User
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
X5266