XC3030L Xilinx, XC3030L Datasheet - Page 46

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
Number
Pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
1
2
3
4
5
6
7
8
9
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
TCLKIN-I/O
PWRDWN
XC3090
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
Number
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
Pin
XC3090 176-Pin TQFP Pinouts
XTAL2(IN)-I/O
M1-RDATA
M0-RTRIG
HDC-I/O
LDC-I/O
INIT-I/O
RESET
M2-I/O
XC3090
GND
GND
GND
VCC
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
2-148
Number
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Pin
89
90
91
92
93
94
95
96
97
98
99
RDY/BUSY-RCLK-I/O
XTAL1(OUT)-BCLKIN-I/O
D0-DIN-I/O
DONE-PG
DOUT-I/O
XC3090
CS0-I/O
CS1-I/O
D7-I/O
D6-I/O
D5-I/O
D4-I/O
D3-I/O
D2-I/O
D1-I/O
CCLK
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Number
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Pin
A1-CS2-I/O
A0-WS-I/O
XC3090
A14-I/O
A13-I/O
A12-I/O
A11-I/O
A10-I/O
A2-I/O
A3-I/O
A15-I/O
A4-I/O
A5-I/O
A6-I/O
A7-I/O
A8-I/O
A9-I/O
GND
GND
GND
VCC
VCC
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–