XC3030L Xilinx, XC3030L Datasheet - Page 6

• Manufacturer Part Number: XC3030L
• Description: Logic Cell Array Families
• Manufacturer: Xilinx

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
The input-buffer portion of each IOB provides threshold
detection to translate external signals applied to the
package pin to internal logic levels. The global input-buffer
threshold of the IOBs can be programmed to be
compatible with either TTL or CMOS levels. The buffered
input signal drives the data input of a storage element,
which may be configured as either a flip-flop or a latch. The
clocking polarity (rising/falling edge-triggered flip-flop,
High/Low transparent latch) is programmable for each of
the two clock lines on each of the four die edges. Note that
a clock line driving a rising edge-triggered flip-flop makes
any latch driven by the same line on the same edge Low -
level transparent and vice versa ( falling edge, High
transparent). All Xilinx primitives in the supported
schematic-entry packages, however, are positive edge-
triggered flip-flops or High transparent latches. When one
clock line must drive flip-flops as well as latches, it is
necessary to compensate for the difference in clocking
polarities with an additional inverter either in the flip-flop
clock input or the latch-enable input. I/O storage elements
are reset during configuration or by the active-Low chip
RESET input. Both direct input (from IOB pin I) and
registered input (from IOB pin Q) signals are available for
interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user IOB includes
a programmable high-impedance pull-up resistor, which
may be selected by the program to provide a constant High
for otherwise undriven package pins. Although the Logic
Cell Array provides circuitry to provide input protection for
electrostatic discharge, normal CMOS handling precau-
tions should be observed.
Flip-flop loop delays for the IOB and logic-block flip-flops
are about 3 ns. This short delay provides good perfor-
mance under asynchronous clock and data conditions.
Short loop delays minimize the probability of a metastable
condition that can result from assertion of the clock during
data transitions. Because of the short-loop-delay charac-
teristic in the Logic Cell Array, the IOB flip-flops can be
used to synchronize external signals applied to the device.
Once synchronized in the IOB, the signals can be used
internally without further consideration of their clock rela-
tive timing, except as it applies to the internal logic and
routing-path delays.
IOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- com-
patible signal levels (8 mA in the XC3100 family). The
network driving IOB pin O becomes the registered or direct
data source for the output buffer. The 3-state control signal
2-108
(IOB) pin FT can control output activity. An open-drain
output may be obtained by using the same signal for
driving the output and 3-state signal nets so that the buffer
output is enabled only for a Low.
Configuration program bits for each IOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 3 control
the following options.
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Summary of I/O Options
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Logic inversion of the output is controlled by one
Logic 3-state control of each IOB output buffer is
Direct or registered output is selectable for each IOB.
Increased output transition speed can be selected to
An internal high-impedance pull-up resistor (active by
Inputs
– Direct
– Flip-flop/latch
– CMOS/TTL threshold (chip inputs)
– Pull-up resistor/open circuit
Outputs
– Direct/registered
– Inverted/not
– 3-state/on/off
– Full speed/slew limited
– 3-state/output enable (inverse)
configuration program bit per IOB.
determined by the states of configuration program bits
which turn the buffer on, or off, or select the output buffer
3-state control interconnection (IOB pin T). When this
IOB output control signal is High, a logic one, the buffer
is disabled and the package pin is high impedance.
When this IOB output control signal is Low, a logic zero,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense (output
enable) is controlled by an additional configuration
program bit.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied (IOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs and
minimize system noise.
default) prevents unconnected inputs from floating.