MC68160C Motorola, MC68160C Datasheet
MC68160C
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MC68160C Summary of contents
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... ENHANCED ETHERNET INTERFACE TRANSCEIVER SEMICONDUCTOR TECHNICAL DATA SUFFIX PLASTIC PACKAGE CASE 848D (TQFP–52) ORDERING INFORMATION Operating Temperature Range Device Package MC68160FB TQFP– MC68160CFB TQFP–52 MC68160BFB – TQFP–52 Motorola, Inc. 1997 Rev 1 1 ...
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... MC68160 MC68160B MC68160C Figure 1. 10Base–T Interface Block Diagram RX Manchester RCLK Decoder MFILT Pulse Conditioner RXLED Carrier RENA Detect CLLED Pulse Conditioner CLSN Mux Pulse TXLED Conditioner TENA Manchester TX Encoder Mux X1 20 MHz X2 Osc TCLK 2 CS0 Jabber CS1 Pre–emphasis Control ...
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... MC68160 MC68160B MC68160C Enhanced Ethernet Serial Transceiver Table 1. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... MC68160 MC68160B MC68160C Pin(s) Symbol Type CONTROLLER INTERFACE 1 RENA O TTL/CMO TTL/CMOS 48 TCLK O TTL/CMOS 49 TENA I TTL 50 RCLK O TTL/CMOS 51 CLSN O TTL/CMOS TTL AUI INTERFACE 21 ACX– ACX+ 23 ARX– ARX+ 25 ATX– ATX+ TWISTED PAIR INTERFACE 31 TPRX– ...
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... MC68160 MC68160B MC68160C Table 1. Pin Function Description (continued) Pin(s) Symbol Type OSCILLATOR AND FREQUENCY MULTIPLIER 12 MFILT I/C CMOS 17 X2 O/C CMOS MODE SELECT 3 CS0 I 4 CS1 TTL 5 CS2 6 LOOP I TTL 9 APORT I TTL 27 TPSQEL I TTL 28 TPFULDL I TTL 29 TPAPCE I TTL 46 TPEN I/O TTL (TTL/CMOS) MOTOROLA ANALOG IC DEVICE DATA ...
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... MC68160 MC68160B MC68160C Table 1. Pin Function Description (continued) Pin(s) Symbol Type STATUS INDICATOR 40 TXLED O TTL/CMOS 41 RXLED O TTL/CMOS 42 CLLED O TTL/CMOS 43 TPLIL O TTL/CMOS 44 TPPLR O TTL/CMOS 45 TPJABB O TTL/CMOS POWER SUPPLY AND GROUND 10 VDDDIV 11 VDDFM 13 GNDFM 14 GNDVCO 15 VDDVCO 20 GNDSUB 7 VDDDIG 8 GNDDIG 18 VDDDIG 19 GNDDIG 30 VDDANA 33 GNDANA ...
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... MC68160 MC68160B MC68160C Motorola Motorola Controller 2 Transceiver MC68160, MC68360 B and C (QUICC ) (EEST ) CS0 1 CS1 1 CS2 0 Pin Pin Sense TCLK TCLK High TX TX High TENA TENA High RCLK RCLK High RX RX High RENA RENA High CLSN CLSN High LOOP 1 N.A. High NOTES: 1. Although LOOP input is not ordinarily classifed as a controller pin included in this table because its sense varies according to the controller used. ...
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... Power Supply Voltage Range Power Supply Ripple (20 kHz to 100 kHz) Power Supply Impulse Noise (Either Polarity) Ambient Operating Temperature Range (MC68160, MC68160C) Ambient Operating Temperature Range (MC68160B) ARX/ACX Input Differential Rise and Fall Time (see Figure 39) ARX Pair Idle Time after Transmission (see Figure 39) ...
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... Differential Input Resistance TWISTED PAIR TRANSMITTER OUTPUTS Differential Output Voltage Pre–Emphasis Level Signal Level (MC68160, MC68160C) Signal Level (MC68160B) Common Mode Output Voltage Range Common Mode Output Voltage in Standby Mode NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). ...
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... Open Circuit Differential Output Impedance TRANSMISSION Mode IDLE Mode Common Mode Output Impedance TRANSMISSION Mode (MC68160, MC68160C) TRANSMISSION Mode (MC68160B) IDLE Mode NOTES: 1. APORT, TPAPCE, CS0, CS1, CS2, TX, LOOP, TPFULDL, TPSQEL and TPEN (In Input Mode). 2. TCLK, RX, RCLK, RENA and CLSN. 3. TPPLR, TPLIL, TPJABB, TXLED, RXLED, CLLED and TPEN (In Output Mode). ...
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... MC68160 MC68160B MC68160C Figure 3. Test Load B1 39 Device V1 RCM 1 Device NOTE: A total of 50 per driver output is required for proper series line termination. This is realized with the 39 external resistors shown in Figures 3, 4 and 5, together with the internal driver output resistance. Figure 6. AUI Common Mode Termination ...
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... TENA Setup Time to TCLK TENA Hold Time to TCLK CONTROLLER RECEIVE SWITCHING RCLK Cycle Time RCLK High Time RCLK Low Time (MC68160, MC68160C) RCLK Low Time (MC68160B) RCLK Rise and Fall Time RX Hold Time from RCLK RX Set–Up Time to RCLK RCLK Delay from RENA ...
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... MC68160 MC68160B MC68160C Figure 9. Receive Phase–Locked–Loop Switching D D CS0 CS1 CS2 1.5V TPRX RENA NOTE: CS0 CS1 CS2 is the logical AND operation and refers to the pins not at Logic 1. Figure 10. Transmit Timing (Motorola Mode 1.5V 1.5V TCLK 1.5V TENA TX Figure 11. Receive Timing (Motorola Start of Frame) 1 ...
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... MC68160 MC68160B MC68160C Figure 12. Receive Timing (Motorola End of Frame) RENA RCLK RX CONTROLLER TRANSMIT SWITCHING (Intel Mode – Support by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time TXD Setup Time to TXC TXD Hold Time to TXC ...
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... MC68160 MC68160B MC68160C CRS RXC RXD CONTROLLER TRANSMIT SWITCHING (Fujitsu Mode – Supported by MC68160 Only) Characteristic TCKN Cycle Time TCKN High and Low Time TCKN Rise and Fall Time TXD Setup Time to TCKN TXD Hold Time to TCKN TEN Setup Time to TCKN ...
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... MC68160 MC68160B MC68160C Figure 16. Receive Timing (Fujitsu Start of Frame) 1.5V XCD t 105 RCKN RXD Figure 17. Receive Timing (Fujitsu End of Frame) XCD RCKN RXD CONTROLLER TRANSMIT SWITCHING (National Mode – Supported by MC68160 Only) Characteristic TXC Cycle Time TXC High and Low Time TXC Rise and Fall Time ...
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... MC68160 MC68160B MC68160C t 111 1.5V TXC t 115 1.5V TXE TXD 1.5V CRS t 125 1.5V RXC RXD MOTOROLA ANALOG IC DEVICE DATA Figure 18. Transmit Timing (National) t 110 3V 1.5V 1.5V 0.8V 0.8V t 111 t 112 t 112 t 113 t 114 1.5V 1.5V Figure 19. Receive Timing (National) t 122 t 120 3V 1.5V 0.8V 1.5V t 121 t 123 t 123 t 124.1 t 124 1.5V t 116 1.5V 1.5V t 126 t 127 1 ...
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... TPTX Precompensation Pulse Width (Notes 2 and 6) (See Figure 25) (MC68160, MC68160C) (MC68160B) RENA Deassert Delay from TENA Deassert when Receiver is inactive Motorola Mode (MC68160, MC68160C) Motorola Mode (MC68160B) Fujitsu Mode (MC68160 Only) National Mode (MC68160 Only) Intel Mode (Note 4) (See Figure 26) (MC68160 Only) TPTX Data– ...
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... MC68160 MC68160B MC68160C Figure 24. TPTX Transmit Timing (Start of Frame) Switching X1 TCLK 1.5V TENA 1 TX 1.5V RENA RX TPTX +/– Differential (Logic Levels) TPTX +/– Differential (Pre–Emphasis) Figure 25. TPTX Transmit Timing (End of Frame) Switching t 136 90% TPTX +/– Differential Figure 26. RENA Deassert Delay from TENA ...
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... MC68160 MC68160B MC68160C t 140 t 139 585mV TP TRANSMIT JABBER SWITCHING Characteristic Max Length of Transmission before Assertion of TPJABB to indicate Jabber Condition CLSN to indicate Jabber Condition Time from End of Jabber Condition to Deassertion: of TPJABB of CLSN TP TRANSMIT SIGNAL QUALITY ERROR TEST SWITCHING CLSN (Signal Quality Error Test) (See Figure 29) ...
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... TPRX to RX Start Up Delay (See Figure 32) TPRX held high from last valid positive transition (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160, MC68160C) (See Figure 33) RENA Deassertion Delay from last valid positive transition of TPRX Pair (MC68160B) TP RECEIVE LINK INTEGRITY SWITCHING ...
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... MC68160 MC68160B MC68160C Figure 32. TPRX Receive Timing (Start of Frame –300mV TPRX+/– RENA RCLK RX Figure 33. RENA Deassertion Delay from Last Valid Positive Transition of TPRX Pair TPRX+/– RENA Figure 34. TP Receive Link Integrity Switching t 201 TPRX TPLIL 22 Bit n Bit n+1 Bit n+2 ...
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... MC68160 MC68160B MC68160C TP COLLISION SWITCHING Characteristic Time from collision (TPRX activity caused assertion of RENA followed by assertion of TENA) to assertion of CLSN Time from end of collision (Deassertion of TENA with uninterrupted TPRX pair activity) to deassertion of CLSN TP FULL DUPLEX SWITCHING TPFULDL assert to collision detect disable (See Figure 36) ...
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... MC68160 MC68160B MC68160C AUI TRANSMIT SWITCHING Characteristic TCLK to ATX Pair Steady State Propagation Delay Output Differential Rise and Fall Times (Measured directly at device pins) ATX Bit Cell Duration center–to–center (Measured directly at device pins) ATX Half–Bit Cell Duration center–to–boundary (Measured directly at device pins) ...
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... Attachment Unit Interface(AUI) and the 10BASE–T Twisted Pair(TP) port. The MC68160’s SIA interface is compatible with most industry controllers and selected by three mode control pins. The MC68160B’s and MC68160C’s SIA interface supports the Motorola MC68360 only. Chip status is supported on all versions indicated by the condition of 6 status indicator pins. All but one are open collector outputs. If the EEST isn’ ...
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... MC68160 MC68160B MC68160C If after approximately 40 ms after AUI transmission has begun, the EEST is still transmitting, the TPJABB pin will assert to signify a jabber condition. Also, the CLLED pin will transition high and low alternately with a 100 ms period. The transmit circuitry is, however, unaffected by the jabber condition, so the communications controller has the responsibility of monitoring and stopping transmission ...
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... TOKO TOKO Application Notes: The following procedure is applicable to all three versions MC68160, MC68160B and MC68160C. References to the MC68160 includes all the versions. Resetting the MC68160 after power up. In some applications, after initial power up, the MC68160 may not be able to transmit or receive data. This is usually caused by the LOOP and TPFULDL control lines being active at the same time ...
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... MC68160 MC68160B MC68160C Figure 41. Î Î Î Î Î Î PE-65424) Î Î Î Î Î Î Î Î Î Î Î Î TXLED RXLED CLLED TPLIL TPPLR TPJABB TPEN GNDCTL TCLK TENA RCLK CLSN (Example ATX+ ATX– ARX+ ARX– ...
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... MC68160 MC68160B MC68160C 4X 0.20 (0.008) H L– VIEW Y 3X –L– –N– –H– –T– 3 SEATING 4X PLANE 0.05 (0.002 VIEW AA MOTOROLA ANALOG IC DEVICE DATA OUTLINE DIMENSIONS FB SUFFIX PLASTIC PACKAGE CASE 848D-03 (TQFP–52) ISSUE C 4X TIPS 0.20 (0.008) T L– ...
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... MC68160 MC68160B MC68160C Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...