MC68HC11E0 Motorola, MC68HC11E0 Datasheet

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MC68HC11E0

Manufacturer Part Number
MC68HC11E0
Description
(MC68HC711E Series) M68HC11E Series Programming Reference Guide
Manufacturer
Motorola
Datasheet

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Reference Guide
M68HC11ERG/AD
Rev. 2, 10/2003
M68HC11E Series
Programming
Reference Guide
Block Diagram
* V
MODE CONTROL
MODA/
PPE
LIR
SYSTEM
applies only to devices with EPROM/OTPROM.
TIMER
PORT A
MODB/
V
STBY
XTAL EXTAL E
BUS EXPANSION
CLOCK LOGIC
OSC
ADDRESS
PORT B
STROBE AND HANDSHAKE
PARALLEL I/O
M68HC11 CPU
IRQ
ADDRESS/DATA
CONTROL
PORT C
INTERRUPT
XIRQ/V
LOGIC
PPE*
RESET
MC68HC11E0
MC68HC11E1
MC68HC11E9
MC68HC711E9
MC68HC11E20
MC68HC711E20
MC68HC811E2
DEVICE
PERIPHERAL
INTERFACE
SERIAL
SPI
CONTROL
PORT D
ROM OR EPROM
(SEE TABLE)
(SEE TABLE)
(SEE TABLE)
RAM
EEPROM
512
512
512
512
768
768
256
COMMUNICATION
RAM
INTERFACE
SERIAL
SCI
ROM
12 K
20 K
A/D CONVERTER
PORT E
© Motorola, Inc., 2003
EPROM
12 K
20 K
EEPROM
2048
V
V
V
V
512
512
512
512
512
DD
SS
RH
RL

Related parts for MC68HC11E0

MC68HC11E0 Summary of contents

Page 1

... PPE IRQ XIRQ/V RESET PPE* INTERRUPT LOGIC M68HC11 CPU SERIAL ADDRESS/DATA PERIPHERAL INTERFACE STROBE AND HANDSHAKE PARALLEL I/O CONTROL PORT C DEVICE MC68HC11E0 MC68HC11E1 MC68HC11E9 MC68HC711E9 MC68HC11E20 MC68HC711E20 MC68HC811E2 ROM OR EPROM (SEE TABLE) EEPROM (SEE TABLE) RAM (SEE TABLE) SERIAL COMMUNICATION V DD INTERFACE ...

Page 2

... M68HC11ERG/AD Devices Covered in This Reference Guide Device MC68HC11E0 MC68HC11E1 MC68HC11E9 MC68HC711E9 MC68HC11E20 MC68HC711E20 MC68HC811E2 M68HC11E Series Programming Model M68HC11E Series Programming Reference Guide RAM ROM EPROM 512 — 512 — 512 12K 512 — 12K 768 20K 768 — ...

Page 3

... Crystal Dependent Timer Summary CPU Clock Cycle Time MOTOROLA M68HC11E Series Programming Reference Guide Selected Crystal (E) (1/E) Pulse Accumulator (in Gated Mode count — 14 overflow — (E/2 ) PR[1: (E/1) 1 count— 16 overflow — (E (E/4) 1 count— 18 overflow — (E (E/8) 1 count— 19 overflow — (E (E/16) 1 count— ...

Page 4

... Clock monitor fail RESET CCR Local Mask Bit Mask — — RIE RIE I TIE TCIE ILIE I SPIE I PAII I PAOVI I TOI I I4/O5I I OC4I I OC3I I OC2I I OC1I I IC3I I IC2I I IC1I I RTII I None X None None None None None None NOCOP None CME None None MOTOROLA ...

Page 5

... M68HC11E Series Memory Maps $0000 EXT $1000 $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 1. Memory Map for MC68HC11E0 $0000 EXT $1000 EXT $B600 EXT $D000 $FFFF EXPANDED BOOTSTRAP Figure 2. Memory Map for MC68HC11E1 MOTOROLA M68HC11E Series Programming Reference Guide 0000 512 BYTES RAM ...

Page 6

... SPECIAL MODES ROM INTERRUPT VECTORS BFFF 12 KBYTES ROM/EPROM FFC0 NORMAL MODES INTERRUPT FFFF VECTORS 768 BYTES RAM 64-BYTE REGISTER BLOCK 8 KBYTES ROM/EPROM * 512 BYTES EEPROM BOOT BFC0 SPECIAL MODES ROM INTERRUPT VECTORS BFFF 12 KBYTES ROM/EPROM * NORMAL FFC0 MODES INTERRUPT FFFF VECTORS MOTOROLA ...

Page 7

... EXT $1000 EXT $F800 $FFFF SINGLE EXPANDED CHIP Figure 5. Memory Map for MC68HC811E2 MOTOROLA M68HC11E Series Programming Reference Guide EXT EXT BOOTSTRAP SPECIAL TEST M68HC11ERG/AD M68HC11E Series Memory Maps 0000 256 BYTES RAM 00FF 1000 64-BYTE REGISTER BLOCK 103F BOOT ...

Page 8

Opcode Maps Page 1 DIR INH INH REL INH ACCA 0000 0001 0010 0011 0100 MSB LSB 0000 0 TEST SBA BRA TSX 0001 1 NOP CBA BRN INS 0010 2 IDIV BRSET BHI PULA 0011 ...

Page 9

Page 2 (18XX) INH INH 0000 0001 0010 0011 MSB LSB 0000 0 TSY 0001 1 0010 2 0011 3 0100 4 0101 5 TYS 0110 6 0111 7 1000 8 INY PULY 1001 9 DEY ...

Page 10

Page 3 (1AXX) 0000 0001 0010 0011 0100 MSB LSB 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C ...

Page 11

Page 4 (CDXX) 0000 0001 0010 0011 MSB LSB 0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1000 8 1001 9 1010 A 1011 B 1100 C 1101 ...

Page 12

... Instruction Opcode BGT 2E BGE 2C BEQ 27 BLE 2F BLT 2D True Instruction Opcode BHI 22 BHS/BCC 24 BEQ 27 BLS 23 BLO/BCS 25 Cycles False Instruction Opcode BPL 2A BNE 26 BVC 28 BCC 24 False Instruction Opcode BLE 2F BLT 2D BNE 26 BGT 2E BGE 2C False Instruction Opcode BLS 23 BL0/BCS 25 BNE 26 BHI 22 BHS/BCC 24 MOTOROLA ...

Page 13

... Left ASLB Arithmetic Shift Left ASLD Arithmetic Shift Left MOTOROLA M68HC11E Series Programming Reference Guide Table 1, which shows all the M68HC11 instructions in all possible Table 1. Instruction Set (Sheet Instruction Addressing Mode Opcode INH 1B INH 3A INH 18 3A ...

Page 14

... MOTOROLA C ∆ ∆ ∆ — — — — — — — — — — — — — — — — — — ...

Page 15

... Adjust Sum to BCD A M – 1 ⇒ M DEC (opr) Decrement Memory Byte A – 1 ⇒ A DECA Decrement Accumulator A B – 1 ⇒ B DECB Decrement Accumulator B MOTOROLA M68HC11E Series Programming Reference Guide Table 1. Instruction Set (Sheet Instruction Addressing Mode Opcode Operand REL 29 rr INH 11 INH 0C INH ...

Page 16

... MOTOROLA ...

Page 17

... B ⇒ B NEGB Two’s Complement B NOP No operation No Operation ⇒ A ORAA (opr) OR Accumulator A (Inclusive ⇒ B ORAB (opr) OR Accumulator B (Inclusive) MOTOROLA M68HC11E Series Programming Reference Guide Table 1. Instruction Set (Sheet Instruction Addressing Mode Opcode IMM 8E DIR 9E EXT BE IND,X AE IND ...

Page 18

... MOTOROLA C — — — — — — — — ∆ ∆ ∆ ∆ ∆ ∆ ∆ — ∆ ∆ ∆ 1 — — ...

Page 19

... Minus TSTA Test A for Zero A – Minus TSTB Test B for Zero B – Minus ⇒ IX TSX Transfer Stack Pointer to X MOTOROLA M68HC11E Series Programming Reference Guide Table 1. Instruction Set (Sheet Instruction Addressing Mode Opcode Operand A DIR EXT ...

Page 20

... MOTOROLA ...

Page 21

... NEXT MAIN INSTR. BSR, BRANCH TO SUBROUTINE MAIN PROGRAM ⇑ PC $8D = BSR SP–1 RTS, RETURN FROM SUBROUTINE MAIN PROGRAM PC $39 = RTS SP+1 ⇑ MOTOROLA M68HC11E Series Programming Reference Guide RTI, RETURN FROM INTERRUPT STACK 7 0 ⇑ SP–2 SP–1 RTN H SP RTN L SWI, SOFTWARE INTERRUPT ...

Page 22

... PC3 PC2 PC1 PC0 PB3 PB2 PB1 PB0 PCL3 PCL2 PCL1 PCL0 DDRC3 DDRC2 DDRC1 DDRC0 PD3 PD2 PD1 PD0 DDRD3 DDRD2 DDRD1 DDRD0 PE3 PE2 PE1 PE0 = Reserved U = Unaffected MOTOROLA ...

Page 23

... Timer Input Capture 3 Register $1014 High (TIC3H) Timer Input Capture 3 Register $1015 Low (TIC3L) Timer Output Compare 1 Register $1016 High (TOC1H) Figure 6. Register and Control Bit Assignments (Sheet MOTOROLA M68HC11E Series Programming Reference Guide Bit Read: FOC1 FOC2 FOC3 Write: ...

Page 24

... Bit Bit 3 Bit 2 Bit 1 Bit Bit 11 Bit 10 Bit 9 Bit Bit 3 Bit 2 Bit 1 Bit OM4 OL4 OM5 OL5 EDG2B EDG2A EDG3B EDG3A I4/O5I IC1I IC2I IC3I Unaffected MOTOROLA ...

Page 25

... Serial Communications Control $102D Register 2 (SCCR2) Serial Communications Status $102E Register (SCSR) 1. SCP2 adds ÷ SCI prescaler and is present only in MC68HC(7)11E20. Figure 6. Register and Control Bit Assignments (Sheet MOTOROLA M68HC11E Series Programming Reference Guide Bit Read: OC1F OC2F ...

Page 26

... Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 EXROW T1 T0 PGM (1) (1) CME CR1 CR0 Bit 3 Bit 2 Bit 1 Bit ROW ERASE EELAT EPGM Unaffected MOTOROLA ...

Page 27

... CCF — Conversion Complete Flag This bit is set after an A/D conversion cycle and cleared when ADCTL is written. Bit 6 — Unimplemented Always reads 0 SCAN — Continuous Scan Control MULT — Multiple Channel/Single Channel Control MOTOROLA M68HC11E Series Programming Reference Guide Bit Read: RBOOT ...

Page 28

... ADR[4:1] ADR2 ADR[4:1] ADR3 ADR[4:1] ADR4 ADR[4:1] — — ADR1 ADR[4:1] ADR2 ADR[4:1] ADR3 ADR[4:1] ADR4 ADR[4: Bit Bit Bit Bit Bit Bit Bit Bit 0 MOTOROLA ...

Page 29

... Any other values for SCP[1:0] are not decoded in the prescaler and the results are unpredictable. ( Shaded areas apply to MC68HC(7)11E20 only. RCKB — SCI Baud Rate Clock Check (TEST) MOTOROLA M68HC11E Series Programming Reference Guide Bit (1) 50% 25% 12.5% (2) 2.500 1 ...

Page 30

... Bit 0 BPRT3 BPRT2 BPRT1 BPRT0 Block Size 32 bytes 64 bytes 128 bytes 288 bytes (1) 512 bytes (1) 512 bytes (1) 512 bytes (1) 512 bytes MOTOROLA ...

Page 31

... Resets: Single chip: Bootstrap: Expanded: U indicates a previously programmed bit. U(L) indicates that the bit resets to the logic level held in the latch prior to reset, but the function of COP is controlled by the DISR bit in TEST1 register. MOTOROLA M68HC11E Series Programming Reference Guide $100B Bit ...

Page 32

... ROMON — ROM/EPROM Enable In single-chip mode, ROMON is forced to 1 out of reset. ROMON does not apply to the MC68HC811E2. For devices with disabled ROM arrays (the MC68HC11E0, MC68HC11E1, MC68L11E0, or MC68L11E1) ROMON must never be set ROM/EPROM removed from the memory map 1 = ROM/EPROM present in the memory map EEON — ...

Page 33

... Data Direction Register for Port D (DDRD) Address: Read: Write: Reset: Bits [7:6] — Unimplemented Always read 0 DDD[5:0] — Data Direction for Port D EPROM Programming Control Register (EPROG) Address: Reset: MOTOROLA M68HC11E Series Programming Reference Guide $103A Bit BIT ...

Page 34

... EXROW can be read and written only in special modes and always returns 0 in normal modes Function Selected 0 0 Normal mode Gate stress 1 1 Drain stress Reserved MOTOROLA ...

Page 35

... IRV off. In special test mode, IRVNE is reset to 1. For the MC68HC811E2, this bit controls only internal read visibility function and has no meaning or effect in single-chip modes. In single-chip modes this bit determines whether the E clock drives out from the chip. MOTOROLA M68HC11E Series Programming Reference Guide $103C Bit 7 6 ...

Page 36

... REG3 REG2 REG1 REG0 RAM[3:0] Address 1000 $8000–$8xFF 1001 $9000–$9xFF 1010 $A000–$AxFF 1011 $B000–$BxFF 1100 $C000–$CxFF 1101 $D000–$DxFF 1110 $E000–$ExFF 1111 $F000–$FxFF MOTOROLA ...

Page 37

... Bits [2:0]— Unimplemented Always reads 0 Output Compare 1 Mask Register (OC1M) Address: Reset: OC1M[7:3] — Output Compare Masks Bits [2:0]— Unimplemented Always reads 0 MOTOROLA M68HC11E Series Programming Reference Guide REG[3:0] Address 0000 $0000–$003F 0001 $1000–$103F 0010 $2000–$203F 0011 $3000– ...

Page 38

... MHz 3.0 MHz $1027 Bit BIT Unaffected by reset Bit 0 (1) (1) CME CR1 CR0 XTAL = 16.0 MHz Timeout – 0 ms, + 8.2 ms 8.19 ms 32.8 ms 131 ms 524 ms 4.0 MHz Bit BIT 0 MOTOROLA ...

Page 39

... Overridden if an output compare function is configured to control the PA3 pin. I4/O5 — Input Capture 4/Output Compare 5 Configure TI4/O5 for input capture or output compare RTR[1:0] — Real-Time Interrupt (RTI) Rate Refer to the following table. MOTOROLA M68HC11E Series Programming Reference Guide $1026 Bit ...

Page 40

... STRA rising edge selected INVB — Invert Strobe Active level is logic Active level is logic 1. 40 M68HC11E Series Programming Reference Guide Bit STAF STAI CWOM HNDS Unaffected Bit 0 OIN PLS EGA INVB MOTOROLA ...

Page 41

... The contents of the corresponding latches are dependent upon the electrical state of the pins during reset. This is indicated by an “I” in the port description. Port B Data Register (PORTB) Address: $1004 Read: Write: Reset: Single Chip or Boot: Expanded or Test: MOTOROLA M68HC11E Series Programming Reference Guide PLS EGA STRB 1 ...

Page 42

... DATA1 DATA0 Bit 0 PCL3 PCL2 PCL1 PCL0 Bit 0 PD3 PD2 PD1 PD0 SDO/MOSI SDI/MISO TxD RxD Bit 0 PE3 PE2 PE1 PE0 AN3 AN2 AN1 AN0 Bit 0 ROW ERASE EELAT EPGM MOTOROLA ...

Page 43

... Serial Communication Interface Control Register 1 (SCCR1) Address: $102C Read: Write: Reset: R8 — Receive Data Bit 8 MOTOROLA M68HC11E Series Programming Reference Guide 0 = EPROM/OTPROM address and data bus configured for normal reads and cannot be programmed 1 = EPROM/OTPROM address and data bus configured for programming and cannot be read ...

Page 44

... Wakeup enabled and receiver interrupts inhibited SBK — Send Break 0 = Break generator off 1 = Break codes generated as long as SBK = 1 44 M68HC11E Series Programming Reference Guide character. Bit TIE TCIE ILIE RIE Bit RWU SBK MOTOROLA ...

Page 45

... This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR with IDLE set and then reading SCDR. MOTOROLA M68HC11E Series Programming Reference Guide Bit 7 6 ...

Page 46

... CPOL, CPHA — Clock Polarity, Clock Phase Refer to SPR[1:0] — SPI Clock Rate Select See the following table. 46 M68HC11E Series Programming Reference Guide Bit SPIE SPE MSTR DWOM Figure Bit 0 CPOL CPHA SPR1 SPR0 MOTOROLA ...

Page 47

... SPIF SET 5. SS NEGATED Figure 7. Serial Peripheral Interface Transfer Format Serial Peripheral Interface Data Register (SPDR) Address: $102A Read: Write: SPI is double buffered in, single buffered out. MOTOROLA M68HC11E Series Programming Reference Guide Frequency at Frequency MHz (Baud) 500 kHz 1.0 MHz 250 kHz 500 kHz 62 ...

Page 48

... Unimplemented Bit BIT Bit BIT Unimplemeted Bit Bit BIT Bit BIT MOTOROLA ...

Page 49

... Always reads 0 OCCR — Output Condition Code Register to Timer Port (Test modes only) CBYP — Timer Divider Chain Bypass (Test modes only) DISR — Disable Reset from COP and Clock Monitor (Special modes only MOTOROLA M68HC11E Series Programming Reference Guide Bit 7 6 ...

Page 50

... Bits [3:0] — Unimplemented Always reads 0 50 M68HC11E Series Programming Reference Guide Bit OC1F OC2F OC3F OC4F Bit TOF RTIF PAOVF PAIF Unimplemented Bit 0 IR/O5F IC1F 1C2F IC3F Bit MOTOROLA ...

Page 51

... Write: Reset: Address: $1013 — Low Read: Write: Reset: TIC3 — Address: $1014 — High Read: Write: Reset: Address: $1015 — Low Read: Write: Reset: MOTOROLA M68HC11E Series Programming Reference Guide Bit BIT 15 BIT 14 BIT 13 BIT Bit 7 ...

Page 52

... OC2I OC3I OC4I Bit TOI RTII PAOVI PAII Unimplemented PR1 PR0 Bit 0 I4/O5I IC1I IC2I IC3I Bit 0 PR1 PR0 Prescaler ÷ 1 ÷ 4 ÷ 8 ÷ 16 MOTOROLA ...

Page 53

... TOC3 — Address: $101A — High Read: Write: Reset: Address: $101B — Low Read: Write: Reset: TOC4 — Address: $101C — High Read: Write: Reset: Read: Write: Reset: MOTOROLA M68HC11E Series Programming Reference Guide Bit BIT 15 BIT 14 BIT 13 BIT Bit 7 ...

Page 54

... EPROM/OTPROM. Figure 9. Pin Assignments for 52-Pin TQFP 46 PE5/AN5 PE1/AN1 45 44 PE4/AN4 43 PE0/AN0 42 PB0/ADDR8 PB1/ADDR9 41 40 PB2/ADDR10 PB3/ADDR11 39 PB4/ADDR12 38 37 PB5/ADDR13 36 PB6/ADDR14 PB7/ADDR15 35 34 PA0/IC3 PD0/RxD 39 IRQ 38 XIRQ PPE RESET 36 PC7/ADDR7/DATA7 35 PC6/ADDR6/DATA6 34 PC5/ADDR5/DATA5 33 PC4/ADDR4/DATA4 32 PC3/ADDR3/DATA3 31 PC2/ADDR2/DATA2 30 PC1/ADDR1/DATA1 29 PC0/ADDR0/DATA0 28 27 XTAL MOTOROLA ...

Page 55

... V MOTOROLA M68HC11E Series Programming Reference Guide 1 PA0/IC3 PB7/ADDR15 5 PB6/ADDR14 6 PB5/ADDR13 7 PB4/ADDR12 8 M68HC11 E SERIES PB3/ADDR11 9 PB2/ADDR10 10 11 PB1/ADDR9 12 PB0/ADDR8 PE0/AN0 13 PE4/AN4 14 PE1/AN1 15 PE5/AN5 16 applies only to devices with EPROM/OTPROM. PPE Figure 10. Pin Assignments for 64-Pin QFP M68HC11ERG/AD M68HC11 E Series Pin Assignments ...

Page 56

... EPROM/OTPROM. PPE Figure 11. Pin Assignments for 56-Pin SDIP PE7/AN7 53 PE3/AN3 52 PE6/AN6 51 PE2/AN2 50 PE5/AN5 49 PE1/AN1 48 PE4/AN4 47 PE0/AN0 46 PB0/ADDR8 45 PB1/ADDR9 44 PB2/ADDR10 43 PB3/ADDR11 42 PB4/ADDR12 41 PB5/ADDR13 40 PB6/ADDR14 39 PB7/ADDR15 38 PA0/IC3 37 PA1/IC2 36 PA2/IC1 35 PA3/OC5/IC4/OC1 34 PA4/OC4/OC1 33 PA5/OC3/OC1 32 PA6/OC2/OC1 31 PA7/PAI/OC1 MOTOROLA ...

Page 57

... MOTOROLA M68HC11E Series Programming Reference Guide PA7/PAI/OC1 1 PA6/OC2/OC1 2 PA5/OC3/OC1 3 PA4/OC4/OC1 4 PA3/OC5/IC4/OC1 5 PA2/IC1 6 PA1/IC2 7 PA0/IC3 8 PB7/ADDR15 9 PB6/ADDR14 10 PB5/ADDR13 11 PB4/ADDR12 MC68HC811E2 12 PB3/ADDR11 13 PB2/ADDR10 14 PB1/ADDR9 15 PB0/ADDR8 16 PE0/AN0 17 PE1/AN1 18 PE2/AN2 19 PE3/AN3 MODB/V 24 STBY Figure 12. Pin Assignments for 48-Pin DIP (MC68HC811E2) ...

Page 58

... $7E ~ DEL _ under $7F delete MOTOROLA ...

Page 59

... Subtract the decimal number found from the original decimal number to get the remaining decimal value. Repeat the procedure using the remaining decimal value for each subsequent hexadecimal digit. MOTOROLA M68HC11E Series Programming Reference Guide Table 3. Hexadecimal to/from Decimal Conversion Bit ...

Page 60

... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such ...

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