RJ80535 Intel, RJ80535 Datasheet - Page 13

• Manufacturer Part Number: RJ80535
• Description: Pentium M Processor
• Manufacturer: Intel

2.1.5
2.1.6
2.2
Intel
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Pentium
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If RESET# is driven active while the processor is in the Sleep state, and held active as specified in
the RESET# pin specification, then the processor will reset itself, ignoring the transition through
Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and
STPCLK# signals should be deasserted immediately after RESET# is asserted to ensure the
processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering an even lower power state, the Deep
Sleep state by asserting the DPSLP# pin. (See
state, the SLP# pin must be deasserted if another asynchronous system bus event needs to occur.
Deep Sleep State
Deep Sleep state is a very low power state the processor can enter while maintaining context. Deep
Sleep state is entered by asserting the DPSLP# pin while in the Sleep state. BCLK may be stopped
during the Deep Sleep state for additional platform level power savings. BCLK stop/restart timings
on Intel 855PM and Intel 855GM chipset-based platforms are as follows:
To re-enter the Sleep state, the DPSLP# pin must be deasserted. BCLK can be re-started after
DPSLP# deassertion as described above. A period of 30 microseconds (to allow for PLL
stabilization) must occur before the processor can be considered to be in the Sleep state. Once in
the Sleep state, the SLP# pin must be deasserted to re-enter the Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions of signals are allowed on the system bus while the
processor is in Deep Sleep state. Any transition on an input signal before the processor has returned
to Stop-Grant state will result in unpredictable behavior.
Deeper Sleep State
The Deeper Sleep state is the lowest power state the processor can enter. This state is functionally
identical to the Deep Sleep state but at a lower core voltage. The control signals to the voltage
regulator to initiate a transition to the Deeper Sleep state are provided on the platform. Please refer
to the platform design guides for details.
Enhanced Intel SpeedStep
The Intel Pentium M processor features Enhanced Intel SpeedStep
implementations of Intel SpeedStep technology, this technology enables the processor to switch
between multiple frequency and voltage points instead of two. This will enable superior
performance with optimal power savings. Switching between states is software controlled unlike
previous implementations where the GHI# pin is used to toggle between two states. The following
are the key features of Enhanced Intel SpeedStep technology:
M Processor Datasheet
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Deep Sleep entry - DPSLP# and CPU_STP# are asserted simultaneously. The platform clock
chip will stop/tristate BCLK within 2 BCLKs +/- a few nanoseconds.
Deep Sleep exit - DPSLP# and CPU_STP# are deasserted simultaneously. The platform clock
chip will drive BCLK to differential DC levels within 2-3 ns and starts toggling BCLK 2-6
BCLK periods later.
Multiple voltage/frequency operating points provide optimal performance at the lowest power.
Voltage/Frequency selection is software controlled by writing to processor MSR’s (Model
Specific Registers) thus eliminating chipset dependency.
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Section
Technology
2.1.5.) While the processor is in the Sleep
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technology. Unlike previous
Low Power Features
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