RJ80535 Intel, RJ80535 Datasheet - Page 20

• Manufacturer Part Number: RJ80535
• Description: Pentium M Processor
• Manufacturer: Intel

Electrical Specifications
3.5
3.6
3.7
20
Catastrophic Thermal Protection
The Intel Pentium M processor supports the THERMTRIP# signal for catastrophic thermal
protection. An external thermal sensor should also be used to protect the processor and the system
against excessive temperatures. Even with the activation of THERMTRIP#, that halts all processor
internal clocks and activity, leakage current can be high enough such that the processor cannot be
protected in all conditions without the removal of power to the processor. If the external thermal
sensor detects a catastrophic processor temperature of 125 °C (maximum), or if the THERMTRIP#
signal is asserted, the VCC supply to the processor must be turned off within
500 ms to prevent permanent silicon damage due to thermal runaway.
Signal Terminations and Unused Pins
All RSVD (RESERVED) pins must remain unconnected. Connection of these pins to V
to any other signal (including each other) can result in component malfunction or incompatibility
with future Intel Pentium M processors. See
location of all RSVD pins.
For reliable operation, always connect unused inputs or bidirectional signals to an appropriate
signal level. Unused active low AGTL+ inputs may be left as no connects if AGTL+ termination is
provided on the processor silicon. Unused active high inputs should be connected through a resistor
to ground (V
For details on signal terminations, please refer to the platform design guides. TAP signal
termination requirements are also discussed in ITP700 Debug Port Design Guide.
The TEST1, TEST2, and TEST3 pins must be left unconnected but should have a stuffing option
connection to V
System Bus Signal Groups
To simplify the following discussion, the system bus signals have been combined into groups by
buffer type. AGTL+ input signals have differential input buffers, which use GTLREF as a reference
level. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the
AGTL+ I/O group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group
as well as the AGTL+ I/O group when driving.
Table 3
Common clock signals which are dependent upon the crossing of the rising edge of BCLK0 and the
falling edge of BCLK1. Source synchronous signals are relative to their respective strobe lines
(data and address) as well as the rising edge of BCLK0. Asychronous signals are still present
(A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle.
identifies which signals are common clock, source synchronous, and asynchronous.
SS
). Unused outputs can be left unconnected.
S S
separately using 1-k
pull-down resistors.
Section 4.2
for a pin listing of the processor and the
Intel
®
Pentium
®
M Processor Datasheet
CC
, V
SS
, or