MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 121

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

6.6.5
The bits in S2SR1 indicate certain conditions in the MI BUS hardware and are automatically
cleared by special acknowledge sequences. The receive related flag bits in S2SR1 (RDRF2, OR2
and NF2) are cleared by a read of this register followed by a read of the transmit/receive data
register. However, only those bits that were set when S2SR1 was read will be cleared by the
subsequent read of the transmit/receive data register.
RDRF2 — Receive data register full flag 2
This bit is set when the contents of the receiver serial shift register have been transferred to the
receiver data register.
The EOF (end-of-frame) during an MI BUS pull-field is a continuous square wave, which will result
in multiple RDRFs. This may be dealt with in any of the following ways:
OR2 — Bit error 2
This bit is set when a push field bit value on the MI BUS does not match the bit value that was
sent. This is known as an MI BUS bit error. OR2 does not generate an interrupt request in MI BUS
mode.
MC68HC11PH8
†
SCI2/MI status 1 (S2SR1)
1 (set)
0 (clear) –
– By clearing the RIE2 mask, ignoring unneeded RDRF2s, initiating a push
– By clearing the RE2 bit when a pull field is complete, followed by setting the RE2
– By disabling the MI BUS.
1 (set)
0 (clear) –
Note that TDRE2 and TC2 will both behave in the same way as during normal SCI
transmissions. The MI BUS will still be receiving when the TC2 bit becomes set, hence any
queued transmission will not start until the current pull field has finished.
See also Section 5.6.4.
field, waiting for TDRE2
bit after the TDRE2
S2SR1 — MI BUS status register 1
–
–
Contents of the receiver serial shift register have been transferred to
the receiver data register.
Contents of the receiver serial shift register have not been
transferred to the receiver data register.
A bit error has been detected.
No bit error has been detected.
MOTOROLA INTERCONNECT BUS (MI BUS)
Address
†
$0054
flag associated with the next push field is asserted;
†
and then clearing the RDRF2;
bit 7
Ñ
bit 6
Ñ
RDRF2
bit 5
bit 4
Ñ
OR2
bit 3
bit 2
NF2
bit 1
Ñ
bit 0
Ñ
MOTOROLA
1100 0000
on reset
State
TPG
6-11
6