MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 122

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MC68HC711PH8

Manufacturer Part Number
MC68HC711PH8
Description
High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
Manufacturer
Motorola
Datasheet
6
NF2 — Noise error flag 2
This bit is set when noise is detected on the receive line during an MI BUS pull field.
6.6.6
RAF2 — Receiver active flag (read only)
6.6.7
This register forms the 8-bit data/address word for the MI push field and contains the 3-bit data
word received as the MI pull field.
R/T[7:0] — Receiver/transmitter data bits [7:0]
READ: Reads access the three bits of pull field data (stored in bits 3–1) of the read-only MI BUS
receive data register. Bits [7:4, 0] are a fixed data pattern when a valid status and end-of-frame is
returned. A valid status is represented by the following data pattern: 0101 xxx1 (bits 7–0), where
‘xxx’ is the status. All ones in the receive data register indicate that an error occurred on the
MI BUS. Bits are received LSB first by the MCU, and the status bits map as shown in the above
table.
WRITE: Writes access the eight bits of the write-only MI BUS transmit data register. MI BUS
devices require a 5-bit data pattern followed by a 3-bit address pattern to be sent during the push
field. The data pattern is mapped to the lowest five bits of the data register and the address to the
highest three bits, as shown in the above table. Thus MI-data[4:0] is written to S2DRL[4:0] and
MI-address[2:0] is written to S2DRL[7:5].
MOTOROLA
6-12
SCI/MI 2 data low (S2DRL)
SCI/MI 2 status 2 (S2SR2)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
S2SR2 — MI BUS2 status register 2
S2DRL — MI BUS2 data register
Noise detected.
No noise detected.
A character is being received.
A character is not being received.
MOTOROLA INTERCONNECT BUS (MI BUS)
Address
Address
$0055
$0057 R7T7B R6T6B R5T5B R4T4B R3T3B R2T2B R1T1B R0T0B undeÞned
bit 7
bit 7
A2
0
0
bit 6
bit 6
A1
0
1
bit 5
bit 5
A0
0
0
bit 4
bit 4
D4
0
1
bit 3
bit 3
S1
D3
0
bit 2
bit 2
S2
D2
0
bit 1
bit 1
S3
D1
0
MC68HC11PH8
RAF2 0000 0000
bit 0
bit 0
D0
1
Push Þeld
Pull Þeld
on reset
on reset
State
State
TPG

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