MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 129

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

CPHA — Clock phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between
master and slave. The CPHA bit selects one of two different clocking protocols. Refer to Figure
7-2 and Section 7.2.1.
SPR1 and SPR0 — SPI clock rate selects
These two bits select the SPI clock rate, as shown in Table 7-1. Note that SPR2 is located in the
OPT2 register, and that its state on reset is zero.
7.5.2
SPIF — SPI interrupt complete flag
SPIF is set upon completion of data transfer between the processor and the external device. If
SPIF goes high, and if SPIE is set, a serial peripheral interrupt is generated. To clear the SPIF bit,
read the SPSR with SPIF set, then access the SPDR. Unless SPSR is read (with SPIF set) first,
attempts to write SPDR are inhibited.
MC68HC11PH8
1 (set)
0 (clear) –
SPI status (SPSR)
SPSR — SPI status register
–
Data transfer to external device has been completed.
No valid completion of data transfer.
SPR[2:0]
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Address
$0029
SERIAL PERIPHERAL INTERFACE
divide ratio
E clock
128
16
32
16
64
2
4
8
Table 7-1 SPI clock rates
SPIF WCOL
bit 7
E = 2MHz
62.5 kHz
31.3 kHz
15.6 kHz
SPI clock frequency ( baud rate) for:
1.0 MHz
500 kHz
125 kHz
250 kHz
125 kHz
bit 6
bit 5
0
E = 3MHz
187.5 kHz
187.5 kHz
93.7 kHz
46.9 kHz
23.4 kHz
1.5 MHz
375 kHz
750kHz
MODF
bit 4
bit 3
0
E = 4MHz
62.5 kHz
31.3 kHz
2.0 MHz
1.0 MHz
250 kHz
125 kHz
500 kHz
250 kHz
bit 2
0
bit 1
0
bit 0
0
MOTOROLA
0000 0000
on reset
State
TPG
7-7
7