MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 131

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

7.5.4
LIRDV — LIR driven (refer to Section 3)
CWOM — Port C wired-OR mode (refer to Section 4)
STRCH — Stretch external accesses (refer to Section 3)
IRVNE — Internal read visibility/not E (refer to Section 3)
In single chip mode this bit determines whether the E clock drives out from the chip.
LSBF — LSB first enable
If this bit is set, data, which is usually transferred MSB first, is transferred LSB first. LSBF does not
affect the position of the MSB and LSB in the data register. Reads and writes of the data register
always have MSB in bit 7.
SPR2 — SPI clock rate select
When set, SPR2 adds a divide-by-4 prescaler to the SPI clock chain. With the two bits in the
SPCR, this bit specifies the SPI clock rate. Refer to Table 7-1.
MC68HC11PH8
System conÞg. options 2 (OPT2)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
OPT2 — System configuration options register 2
–
–
–
–
–
–
Enable LIR push-pull drive.
LIR not driven on MODA/LIR pin.
Port C outputs are open-drain.
Port C operates normally.
Off-chip accesses are extended by one E clock cycle.
Normal operation.
Data from internal reads is driven out of the external data bus.
No visibility of internal reads on external bus.
E pin is driven low.
E clock is driven out from the chip.
SPI1 data is transferred LSB first.
SPI1 data is transferred MSB first.
Address
$0038
SERIAL PERIPHERAL INTERFACE
LIRDV CWOM STRCH IRVNE LSBF
bit 7
bit 6
bit 5
bit 4
bit 3
SPR2 EXT4X DISE x00x 0000
bit 2
bit 1
bit 0
MOTOROLA
on reset
State
TPG
7-9
7