MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 145

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8.1.4
Output compare
Use the output compare (OC) function to program an action to occur at a specific time — when
the 16-bit counter reaches a specified value. For each of the five output compare functions, there
is a separate 16-bit compare register and a dedicated 16-bit comparator. The value in the compare
register is compared to the value of the free-running counter on every bus cycle. When the
compare register matches the counter value, an output compare status flag is set. The flag can be
used to initiate the automatic actions for that output compare function.
To produce a pulse of a specific duration, write a value to the output compare register that
represents the time the leading edge of the pulse is to occur. The output compare circuit is
configured to set the appropriate output either high or low, depending on the polarity of the pulse
being produced. After a match occurs, the output compare register is reprogrammed to change
the output pin back to its inactive level at the next match. A value representing the width of the
pulse is added to the original value, and then written to the output compare register. Because the
pin state changes occur at specific values of the free-running counter, the pulse width can be
controlled accurately at the resolution of the free-running counter, independent of software
latency. To generate an output signal of a specific frequency and duty cycle, repeat this
pulse-generating procedure.
There are four 16-bit read/write output compare registers: TOC1, TOC2, TOC3, and TOC4, and
the TI4/O5 register, which functions under software control as either IC4 or OC5. Each of the OC
registers is set to $FFFF on reset. A value written to an OC register is compared to the
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free-running counter value during each E clock cycle. If a match is found, the particular output
compare flag is set in timer interrupt flag register 1 (TFLG1). If that particular interrupt is enabled
in the timer interrupt mask register 1 (TMSK1), an interrupt is generated. In addition to an interrupt,
a specified action can be initiated at one or more timer output pins. For OC[5:2], the pin action is
controlled by pairs of bits (OMx and OLx) in the TCTL1 register. The output action is taken on each
successful compare, regardless of whether or not the OCxF flag in the TFLG1 register was
previously cleared.
OC1 is different from the other output compares in that a successful OC1 compare can affect any
or all five of the OC pins. The OC1 output action taken when a match is found is controlled by two
8-bit registers with three bits unimplemented: the output compare 1 mask register, OC1M, and the
output compare 1 data register, OC1D. OC1M specifies which port A outputs are to be used, and
OC1D specifies what data is placed on these port pins.
TPG
MC68HC11PH8
TIMING SYSTEM
MOTOROLA
8-11