MC68HC711PH8 Motorola, MC68HC711PH8 Datasheet - Page 153

• Manufacturer Part Number: MC68HC711PH8
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcomputer Unit
• Manufacturer: Motorola

8.1.5
The real-time interrupt (RTI) feature, used to generate hardware interrupts at a fixed periodic rate,
has two possible clock sources. When the PLL clock generation is not used (VDDSYN low), the
RTI function is clocked by the 16-bit free-running counter (ST4XCK/2
generation is used (VDDSYN high), the RTI clock source is the underflow of the 8-bit modulus
timer A (CLK64). This ensures that the RTI interrupt rate is unaffected by changes made to the
bus speed by the PLL circuit. See Figure 8-1 and Figure 8-2. The RTI clock rate is controlled and
configured by two bits (RTR1 and RTR0) in the pulse accumulator control (PACTL) register. The
different rates available are a product of the source frequency and the value of bits RTR[1:0]. If
VDDSYN is low, the source frequency, ST4XCK/2
high, the source frequency, CLK64, can be divided by 1,2,4 or 64. Refer to Table 8-2 and Table
8-3 which show examples of periodic real-time interrupt rates. The RTII bit in the TMSK2 register
enables the interrupt capability.
Note:
Either clock source causes the time between successive RTI timeouts to be a constant that is
independent of the software latency associated with flag clearing and service. For this reason, an
RTI period starts from the previous timeout, not from when RTIF is cleared.
Every timeout causes the RTIF bit in TFLG2 to be set, and if RTII is set, an interrupt request is
generated. After reset, one entire RTI period elapses before the RTIF flag is set for the first time.
Refer to the TMSK2, TFLG2, and PACTL registers.
MC68HC11PH8
The values in Table 8-3 assume that the 8-bit modulus timer is loaded to give an
EXTALi/2
to EXTALi/4080 (see Section 8.3.1).
RTR[1:0]
RTR[1:0]
Real-time interrupt
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
8
prescaler value. Other prescaler values are possible, in the range EXTALi/4
ST4XCK = 12MHz
EXTALi = 640kHz EXTALi = 32.768kHz
10.923ms
21.845ms
2.731ms
5.461ms
Table 8-2 RTI periodic rates (PLL disabled)
Table 8-3 RTI periodic rates (PLL enabled)
25.6ms
0.4ms
0.8ms
1.6ms
ST4XCK = 8MHz
TIMING SYSTEM
16.384ms
32.768ms
4.096ms
8.192ms
15.63ms
31.25ms
7.81ms
500ms
15
, can be divided by 1,2,4 or 8. If VDDSYN is
ST4XCK = 4MHz
EXTALi = 32kHz
16.384ms
32.768ms
65.536ms
8.192ms
16.0ms
32.0ms
512ms
8.0ms
ST4XCK = xMHz
EXTALi = xkHz
15
2
2
2
2
2
2
15
16
17
18
2
2
). When the PLL clock
10
14
8
9
/ST4XCK
/ST4XCK
/ST4XCK
/ST4XCK
/EXTALi
/EXTALi
/EXTALi
/EXTALi
MOTOROLA
TPG
8-19
8